Joon-Yeong Lee

A 0.87 W Transceiver IC for 100 Gigabit Ethernet in 40 nm CMOS

This paper describes a low-power 100 Gigabit Ethernet transceiver IC compliant with IEEE802.3ba 100GBASE-LR4 in 40 nm CMOS. The proposed bidirectional full-duplex transceiver IC contains a total of eight 28 Gb/s CDRs. Each CDR lane incorporates phase-rotator-based delay- and phase-locked loop (D/PLL) architecture for enhanced jitter filtering. All the CDR lanes operate independently while sharing a single voltage-controlled oscillator and supporting referenceless clock acquisition. To reduce power consumption, a multidrop clock distribution scheme with single on-chip transmission-line (T-line) and quadrate RX and TX schemes without CML logic gates are incorporated. Embedded built-in self-test modules featuring a random accumulation jitter generator enables bit error rate (BER) and jitter tolerance self tests without any external equipment. The TX featuring a three-tap pre-emphasis provides a variable output swing ranging from 478 mVppd to 1.06 Vppd. RX equalizers employing a continuous-time linear equalizer and a one-tap decision feedback equalizer compensate for the channel loss up to 25 dB at the Nyquist rate. The measured RX input sensitivity for a BER of 10 -12 is 42 mVppd. The proposed IC consumes only 0.87 W at 28.0 Gb/s with a BER less than 10 -15 on PRBS31 testing. The power efficiency of the proposed transceiver is 3.9 mW/Gb/s, which is the best among the efficiencies achieved by recently published 25 Gb/s transceivers.

Application of Kalman Gain for Minimum Mean-Squared Phase-Error Bound in Bang-Bang CDRs

This paper presents the minimum bound of the mean-squared phase-error of a bang-bang (BB) clock-and-data recovery (CDR) circuit under the condition of random phase tracking. An analogy between the Kalman filter and a linearized BB CDR is utilized for the derivation. The effects of demultiplexing, loop latency, and granular jitter are considered in the analysis to reflect reality. The validity of the theoretical analysis is supported by behavioral time domain simulation results.

Phase-Rotator-Based All-Digital Phase-Locked Loop for a Spread-Spectrum Clock Generator

A phase-rotator-based all-digital phase-locked loop for spread-spectrum clock generation is presented. It combines a dual-tone triangular and a random modulation profile to achieve a balance between electromagnetic interference reduction and broadband jitter generation. The test chip, fabricated using a 90-nm CMOS process, achieves a 43-dB total EMI reduction at the resolution bandwidth of 100 Hz without incurring a notable bit-error-rate penalty at the receivers side and consuming only 15.8 mW at 6 GHz from a 1-V supply.

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A four-parallel 10-Gb/s referenceless-and-masterless phase rotator-based transceiver is presented. Entire lanes operate independently just like the conventional voltage-controlled-oscillator-based parallel referenceless designs while saving power and area. The measured recovered-clock jitter in each lane is 1.24 psrms and the transceiver surpasses the OC-192 jitter-tolerance specification. The power efficiency of the proposed parallel transceiver fabricated in a 90-nm CMOS process is 6.325 mW/(Gb/s).

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This paper describes a 28-Gb/s receiver IC with self-contained adaptive equalization and sampling point control using an on-chip stochastic sigma-tracking eye-opening monitor (SSEOM). The proposed SSEOM accurately detects the bit-error-rate (BER)-related eye contour efficiently without the use of an external microcontroller. The SSEOM determines the BER-optimal sampling point and equalizer coefficients on the basis of pattern-filtered eye diagrams. It also features a background adaptation scheme for robust long-term operation by tracking temperature variations and device aging. The proposed SSEOM is integrated in a 28-Gb/s receiver that is designed to compensate for channel loss up to 25 dB at the Nyquist rate by using a continuous time linear equalizer (CTLE) and a one-tap decision feedback equalizer (DFE) together with an one-tap pre-emphasis at a transmitter. The time required for complete adaptation and the total power consumption are 364 ms and 43.9 mW, respectively. The proposed 28-Gb/s receiver is fabricated in 40 nm CMOS.

-Gb/s Referenceless-and-Masterless Phase Rotator-Based Parallel Transceiver in 90-nm CMOS

An automatic loop gain control algorithm (ALGC) for a bang-bang (BB) clock and data recovery (CDR) is proposed. The proposed algorithm finds the optimum loop gain using the autocorrelation of a BBPD output signal for minimum MSE performance. Mathematical proof of the algorithm is presented for both rotator-based and VCO-based CDRs with finite loop delay. A 25 Gb/s transceiver IC is fabricated using a 40 nm CMOS process to validate the performance of the algorithm. The power consumptions of TX and RX are 37.8 mW and 46.8 mW, respectively and the synthesized area implementing a digital loop filter together with the proposed ALGC occupies 140 μm × 170 μm.

A 28-Gb/s Receiver With Self-contained Adaptive Equalization and Sampling Point Control Using Stochastic Sigma-Tracking Eye-Opening Monitor

This paper presents the industrys first low-power 100-Gigabit Ethernet (GbE) multi-link gearbox (MLG) IC, which facilitates transport of independent 10-GbE and 40-GbE signals to 4×25G physical layers implementing 100GBASE-R. The IC consumes only 1.37-W while implementing complicated reverse gearbox functionality. The measured TX jitter from the 25-Gb/s lane is 1.6-psrms, and the recovered clock jitter is 0.5-psrms. The measured RX input sensitivity for a BER 10-12 is 42-mVppd. The proposed gearbox IC, fabricated in a 40nm CMOS process, occupies 3.7×3.4-mm2. The power consumption of RX and TX in 25G interfaces are 47-mW and 51-mW, respectively, and those of a 10G interfaces are 24-mW and 25-mW, respectively. Gearbox functionalities are verified with embedded self-test logics.

An Automatic Loop Gain Control Algorithm for Bang-Bang CDRs

A phase interpolator (PI)-based 10 × 10 Gb/s bootstrap transceiver for referenceless and lane-independent operation is presented. PI output clock signals phase locked to the input data are used as reference clock signals for frequency locking the voltage-controlled oscillator (VCO). The VCO clock signal is then redistributed to the PIs, triggering the bootstrapping between the VCO and the PIs. All lanes operate independently as in VCO-based parallel referenceless designs while saving power and area. The measured recovered-data jitter in each lane is 0.93 psrms and the transceiver passes the OC-192 jitter-tolerance specification. A flip-chip packaged test chip is fabricated in a 40 nm CMOS technology. The test chip achieves figure-of-merits (mW/Gbps) of 2.03 and 2.13 for the receiver and the transmitter, respectively.

A 100-GbE reverse gearbox IC in 40nm CMOS for supporting legacy 10- and 40-GbE standards

A phase interpolator (PI)-based 10 × 10 Gb/s bootstrap transceiver for reference-less and lane-independent operation is presented. PI output clock signals that are phase locked to the input data are used for the voltage-controlled oscillator (VCO) frequency locking. The VCO clock signal is then redistributed to the PIs, which triggers bootstrapping between the VCO and PIs. Entire lanes operate independently as in VCO-based parallel reference-less designs, but without performance penalties and with power and area savings. The measured recovered-data jitter in each lane is 0.93 psrms and the transceiver passes the OC-192 jitter-tolerance specification. A flip-chip packaged test chip is fabricated in a 40 nm CMOS technology, having receiver and transmitter figure-of-merits (mW/Gb/s) of 2.03 and 2.13, respectively.