Hyun-jong Chung

Graphene Barristor, a Triode Device with a Gate-Controlled Schottky Barrier

Updating the Triode with Graphene In early electronics, the triode—a vacuum device that combined a diode and an electrical grid—was used to control and amplify signals, but was replaced in most applications by solid-state silicon electronics. One characteristic of silicon-metal interfaces is that the Schottky barrier created—which acts as a diode—does not change with the work function of the metal—the Fermi level is pinned by the presence of surface states. Yang et al. (p. 1140, published online 17 May) now show that for a graphene-silicon interface, Fermi-level pinning can be overcome and a triode-type device with a variable barrier, a “barristor,” can be made and used to create devices such as inverters. The absence of defects and surface oxides at a graphene/silicon interface enables voltage control of graphene devices. Despite several years of research into graphene electronics, sufficient on/off current ratio Ion/Ioff in graphene transistors with conventional device structures has been impossible to obtain. We report on a three-terminal active device, a graphene variable-barrier “barristor” (GB), in which the key is an atomically sharp interface between graphene and hydrogenated silicon. Large modulation on the device current (on/off ratio of 105) is achieved by adjusting the gate voltage to control the graphene-silicon Schottky barrier. The absence of Fermi-level pinning at the interface allows the barrier’s height to be tuned to 0.2 electron volt by adjusting graphene’s work function, which results in large shifts of diode threshold voltages. Fabricating GBs on respective 150-mm wafers and combining complementary p- and n-type GBs, we demonstrate inverter and half-adder logic circuits.

A role for graphene in silicon-based semiconductor devices

As silicon-based electronics approach the limit of improvements to performance and capacity through dimensional scaling, attention in the semiconductor field has turned to graphene, a single layer of carbon atoms arranged in a honeycomb lattice. Its high mobility of charge carriers (electrons and holes) could lead to its use in the next generation of high-performance devices. Graphene is unlikely to replace silicon completely, however, because of the poor on/off current ratio resulting from its zero bandgap. But it could be used to improve silicon-based devices, in particular in high-speed electronics and optical modulators.

Robust bi-stable memory operation in single-layer graphene ferroelectric memory

With the motivation of realizing an all graphene-based circuit for low power, we present a reliable nonvolatile graphene memory device, single-layer graphene (SLG) ferroelectric field-effect transistor (FFET). We demonstrate that exfoliated single-layer graphene can be optically visible on a ferroelectric lead-zirconate-titanate (PZT) substrate and observe a large memory window that is nearly equivalent to the hysteresis of the PZT at low operating voltages in a graphene FFET. In comparison to exfoliated graphene, FFETs fabricated with chemical vapor deposited (CVD) graphene exhibit enhanced stability through a bi-stable current state operation with long retention time. In addition, we suggest that the trapping/de-trapping of charge carriers in the interface states is responsible for the anti-hysteresis behavior in graphene FFET on PZT. V C 2011 American Institute of Physics. [doi:10.1063/1.3619816] Graphene is considered to be an exceptional material with high potential for future electronics, owing to its excellent electronic properties; 1 linear electron energy dispersion, and high room temperature mobility. If feasible, an all graphene-based circuit, including logic, analog, and memory devices, would be of great interest to further extend the performance of current Si-based electronics. Among various device applications, graphene based memory structures are still in their infancy in comparison to its logic and analog applications. To date, graphene memory has been demonstrated through chemical modification, 2 filament-type memristor, 3 nanomechanical switch, 4 and graphene FFETs. 5‐7 In graphene FFETs, however, the ambipolar conduction leads to undesirable on/off states for memory applications. Moreover, the absence of an electronic bandgap and controlled doping makes it difficult to resolve such issues. Therefore, a systematic study of graphene FFET is beneficial to realize graphene-based memory structures. In this Letter, we investigate graphene/PZT FFET structures using exfoliated- and CVD-SLG and their mechanism of operation. We show that exfoliated SLG can be optically identified on a PZT substrate and exhibit a hysteresis of the Vshaped conductance with a large memory window at low operating gate voltages. We compare exfoliated- with CVDSLG FFETs and show that devices made of CVD-SLG exhibit a robust bi-stable current state with a long retention time. In order to construct the SLG FFET, we first engineered a ferroelectric substrate to identify SLG. Previously, we have demonstrated that SLG is invisible under the optical micro

The interlayer screening effect of graphene sheets investigated by Kelvin probe force microscopy

We report on the interlayer screening effect of graphene using Kelvin probe force microscopy (KPFM). By using a gate device configuration that enables the supply of electronic carriers in graphene sheets, the vertical screening properties were studied from measuring the surface potential gradient. The results show layer-dependence of graphene sheets, as the number of graphene layers increases, the surface potential decreases exponentially. In addition, we calculate the work function-related information of the graphene layers using KPFM.

Graphene and Thin-Film Semiconductor Heterojunction Transistors Integrated on Wafer Scale for Low-Power Electronics

Graphene heterostructures in which graphene is combined with semiconductors or other layered 2D materials are of considerable interest, as a new class of electronic devices has been realized. Here we propose a technology platform based on graphene-thin-film-semiconductor-metal (GSM) junctions, which can be applied to large-scale and power-efficient electronics compatible with a variety of substrates. We demonstrate wafer-scale integration of vertical field-effect transistors (VFETs) based on graphene-In-Ga-Zn-O (IGZO)-metal asymmetric junctions on a transparent 150 × 150 mm(2) glass. In this system, a triangular energy barrier between the graphene and metal is designed by selecting a metal with a proper work function. We obtain a maximum current on/off ratio (Ion/Ioff) up to 10(6) with an average of 3010 over 2000 devices under ambient conditions. For low-power logic applications, an inverter that combines complementary n-type (IGZO) and p-type (Ge) devices is demonstrated to operate at a bias of only 0.5 V.

Nonmonotonic temperature dependent transport in graphene grown by chemical vapor deposition

Temperature-dependent resistivity of graphene grown by chemical vapor deposition (CVD) is investigated. We observe in low mobility CVD graphene device a strong insulating behavior at low temperatures and a metallic behavior at high temperatures manifesting a non-monotonic in the temperature dependent resistivity.This feature is strongly affected by carrier density modulation. To understand this anomalous temperature dependence, we introduce thermal activation of charge carriers in electron-hole puddles induced by randomly distributed charged impurities. Observed temperature evolution of resistivity is then understood from the competition among thermal activation of charge carriers, temperature-dependent screening and phonon scattering effects. Our results imply that the transport property of transferred CVD-grown graphene is strongly influenced by the details of the environment

Graphene for true Ohmic contact at metal-semiconductor junctions.

The rectifying Schottky characteristics of the metal-semiconductor junction with high contact resistance have been a serious issue in modern electronic devices. Herein, we demonstrated the conversion of the Schottky nature of the Ni-Si junction, one of the most commonly used metal-semiconductor junctions, into an Ohmic contact with low contact resistance by inserting a single layer of graphene. The contact resistance achieved from the junction incorporating graphene was about 10(-8) ~ 10(-9) Ω cm(2) at a Si doping concentration of 10(17) cm(-3).

Passivation of Metal Surface States: Microscopic Origin for Uniform Monolayer Graphene by Low Temperature Chemical Vapor Deposition

Scanning tunneling microscopy (STM) and density functional theory (DFT) calculations were used to investigate the surface morphology and electronic structure of graphene synthesized on Cu by low temperature chemical vapor deposition (CVD). Periodic line patterns originating from the arrangements of carbon atoms on the Cu surface passivate the interaction between metal substrate and graphene, resulting in flawless inherent graphene band structure in pristine graphene/Cu. The effective elimination of metal surface states by the passivation is expected to contribute to the growth of monolayer graphene on Cu, which yields highly enhanced uniformity on the wafer scale, making progress toward the commercial application of graphene.

Probing nanoscale conductance of monolayer graphene under pressure

The correlation between charge transport and mechanical deformation of the single layer graphene layer was studied with conductive probe atomic force microscopy/friction force microscopy in ultra-high vacuum. By measuring the current and friction on a graphene layer that is under mechanical stress, we identify crossover of two regimes in the current density that depend on the applied pressure. We suggest that the difference in work function under mechanical deformation as well as a change in the density of state and formation of a dipole field are responsible for this crossover behavior.

Graphene Interconnect Lifetime: A Reliability Analysis

Understanding the breakdown current density is not enough for establishing the reliability performance of graphene interconnects. It is more important to know how graphene wires degrade with time under constant current stress and how that compares with conventional interconnects. This letter investigates the lifetime of graphene interconnect under constant high current stress. Under a stress current density of 20 MA/cm2 at 250°C exposed to air, the mean time to fail of a 3-μm-wide 100-μm-long graphene interconnect is approximately 6 h, slightly worse than the extrapolated electromigration lifetime of a copper interconnect capped with CoWP at the same stress current density. Raman study shows that the interconnect failure is mainly caused by defect formation due to graphene oxidation. This suggests that optimizing the capping material for graphene interconnect will substantially improve the reliability lifetime of graphene interconnects.