Jinseong Heo

Graphene Barristor, a Triode Device with a Gate-Controlled Schottky Barrier

Updating the Triode with Graphene In early electronics, the triode—a vacuum device that combined a diode and an electrical grid—was used to control and amplify signals, but was replaced in most applications by solid-state silicon electronics. One characteristic of silicon-metal interfaces is that the Schottky barrier created—which acts as a diode—does not change with the work function of the metal—the Fermi level is pinned by the presence of surface states. Yang et al. (p. 1140, published online 17 May) now show that for a graphene-silicon interface, Fermi-level pinning can be overcome and a triode-type device with a variable barrier, a “barristor,” can be made and used to create devices such as inverters. The absence of defects and surface oxides at a graphene/silicon interface enables voltage control of graphene devices. Despite several years of research into graphene electronics, sufficient on/off current ratio Ion/Ioff in graphene transistors with conventional device structures has been impossible to obtain. We report on a three-terminal active device, a graphene variable-barrier “barristor” (GB), in which the key is an atomically sharp interface between graphene and hydrogenated silicon. Large modulation on the device current (on/off ratio of 105) is achieved by adjusting the gate voltage to control the graphene-silicon Schottky barrier. The absence of Fermi-level pinning at the interface allows the barrier’s height to be tuned to 0.2 electron volt by adjusting graphene’s work function, which results in large shifts of diode threshold voltages. Fabricating GBs on respective 150-mm wafers and combining complementary p- and n-type GBs, we demonstrate inverter and half-adder logic circuits.

Robust bi-stable memory operation in single-layer graphene ferroelectric memory

With the motivation of realizing an all graphene-based circuit for low power, we present a reliable nonvolatile graphene memory device, single-layer graphene (SLG) ferroelectric field-effect transistor (FFET). We demonstrate that exfoliated single-layer graphene can be optically visible on a ferroelectric lead-zirconate-titanate (PZT) substrate and observe a large memory window that is nearly equivalent to the hysteresis of the PZT at low operating voltages in a graphene FFET. In comparison to exfoliated graphene, FFETs fabricated with chemical vapor deposited (CVD) graphene exhibit enhanced stability through a bi-stable current state operation with long retention time. In addition, we suggest that the trapping/de-trapping of charge carriers in the interface states is responsible for the anti-hysteresis behavior in graphene FFET on PZT. V C 2011 American Institute of Physics. [doi:10.1063/1.3619816] Graphene is considered to be an exceptional material with high potential for future electronics, owing to its excellent electronic properties; 1 linear electron energy dispersion, and high room temperature mobility. If feasible, an all graphene-based circuit, including logic, analog, and memory devices, would be of great interest to further extend the performance of current Si-based electronics. Among various device applications, graphene based memory structures are still in their infancy in comparison to its logic and analog applications. To date, graphene memory has been demonstrated through chemical modification, 2 filament-type memristor, 3 nanomechanical switch, 4 and graphene FFETs. 5‐7 In graphene FFETs, however, the ambipolar conduction leads to undesirable on/off states for memory applications. Moreover, the absence of an electronic bandgap and controlled doping makes it difficult to resolve such issues. Therefore, a systematic study of graphene FFET is beneficial to realize graphene-based memory structures. In this Letter, we investigate graphene/PZT FFET structures using exfoliated- and CVD-SLG and their mechanism of operation. We show that exfoliated SLG can be optically identified on a PZT substrate and exhibit a hysteresis of the Vshaped conductance with a large memory window at low operating gate voltages. We compare exfoliated- with CVDSLG FFETs and show that devices made of CVD-SLG exhibit a robust bi-stable current state with a long retention time. In order to construct the SLG FFET, we first engineered a ferroelectric substrate to identify SLG. Previously, we have demonstrated that SLG is invisible under the optical micro

Graphene and Thin-Film Semiconductor Heterojunction Transistors Integrated on Wafer Scale for Low-Power Electronics

Graphene heterostructures in which graphene is combined with semiconductors or other layered 2D materials are of considerable interest, as a new class of electronic devices has been realized. Here we propose a technology platform based on graphene-thin-film-semiconductor-metal (GSM) junctions, which can be applied to large-scale and power-efficient electronics compatible with a variety of substrates. We demonstrate wafer-scale integration of vertical field-effect transistors (VFETs) based on graphene-In-Ga-Zn-O (IGZO)-metal asymmetric junctions on a transparent 150 × 150 mm(2) glass. In this system, a triangular energy barrier between the graphene and metal is designed by selecting a metal with a proper work function. We obtain a maximum current on/off ratio (Ion/Ioff) up to 10(6) with an average of 3010 over 2000 devices under ambient conditions. For low-power logic applications, an inverter that combines complementary n-type (IGZO) and p-type (Ge) devices is demonstrated to operate at a bias of only 0.5 V.

Graphene for true Ohmic contact at metal-semiconductor junctions.

The rectifying Schottky characteristics of the metal-semiconductor junction with high contact resistance have been a serious issue in modern electronic devices. Herein, we demonstrated the conversion of the Schottky nature of the Ni-Si junction, one of the most commonly used metal-semiconductor junctions, into an Ohmic contact with low contact resistance by inserting a single layer of graphene. The contact resistance achieved from the junction incorporating graphene was about 10(-8) ~ 10(-9) Ω cm(2) at a Si doping concentration of 10(17) cm(-3).

Passivation of Metal Surface States: Microscopic Origin for Uniform Monolayer Graphene by Low Temperature Chemical Vapor Deposition

Scanning tunneling microscopy (STM) and density functional theory (DFT) calculations were used to investigate the surface morphology and electronic structure of graphene synthesized on Cu by low temperature chemical vapor deposition (CVD). Periodic line patterns originating from the arrangements of carbon atoms on the Cu surface passivate the interaction between metal substrate and graphene, resulting in flawless inherent graphene band structure in pristine graphene/Cu. The effective elimination of metal surface states by the passivation is expected to contribute to the growth of monolayer graphene on Cu, which yields highly enhanced uniformity on the wafer scale, making progress toward the commercial application of graphene.

Two-terminal floating-gate memory with van der Waals heterostructures for ultrahigh on/off ratio

Concepts of non-volatile memory to replace conventional flash memory have suffered from low material reliability and high off-state current, and the use of a thick, rigid blocking oxide layer in flash memory further restricts vertical scale-up. Here, we report a two-terminal floating gate memory, tunnelling random access memory fabricated by a monolayer MoS2/h-BN/monolayer graphene vertical stack. Our device uses a two-terminal electrode for current flow in the MoS2 channel and simultaneously for charging and discharging the graphene floating gate through the h-BN tunnelling barrier. By effective charge tunnelling through crystalline h-BN layer and storing charges in graphene layer, our memory device demonstrates an ultimately low off-state current of 10−14 A, leading to ultrahigh on/off ratio over 109, about ∼103 times higher than other two-terminal memories. Furthermore, the absence of thick, rigid blocking oxides enables high stretchability (>19%) which is useful for soft electronics.

Band gap opening by two-dimensional manifestation of peierls instability in graphene.

Using first-principles calculations of graphene having high-symmetry distortion or defects, we investigate band gap opening by chiral symmetry breaking, or intervalley mixing, in graphene and show an intuitive picture of understanding the gap opening in terms of local bonding and antibonding hybridizations. We identify that the gap opening by chiral symmetry breaking in honeycomb lattices is an ideal two-dimensional (2D) extension of the Peierls metal-insulator transition in 1D linear lattices. We show that the spontaneous Kekule distortion, a 2D version of the Peierls distortion, takes place in biaxially strained graphene, leading to structural failure. We also show that the gap opening in graphene antidots and armchair nanoribbons, which has been usually attributed to quantum confinement effects, can be understood with the chiral symmetry breaking.

Characteristics of CVD graphene nanoribbon formed by a ZnO nanowire hardmask

A graphene nanoribbon (GNR) is an important basic structure to open a bandgap in graphene. The GNR processes reported in the literature are complex, time-consuming, and expensive; moreover, the device yield is relatively low. In this paper, a simple new process to fabricate a long and straight graphene nanoribbon with a high yield has been proposed. This process utilizes CVD graphene substrate and a ZnO nanowire as the hardmask for patterning. 8 µm long and 50-100 nm wide GNRs were successfully demonstrated in high density without any trimming, and ∼ 10% device yield was realized with a top-down patterning process. After passivating the surfaces of the GNRs using a low temperature atomic layer deposition (ALD) of Al(2)O(3), high performance GNR MOSFETs with symmetric drain-current-gate-voltage (I(d)-V(g)) curves were demonstrated and a field effect mobility up to ∼ 1200 cm(2) V(-1) s(-1) was achieved at V(d) = 10 mV.

RF performance of pre-patterned locally-embedded-back-gate graphene device

We measured Radio-Frequency (RF) performance of devices with graphene grown using low temperature Inductively-Coupled Plasma Chemical Vapor Deposition (ICP-CVD) method on 6-inch wafer for the first time. To remove the coupling of electrode in-plane, we introduced locally-embedded-back-gate using TiN metal. The symmetric structure of 2-gate fingers was adopted to reduce misalign issue during fabrication of the structure with underlap between Gate and Source/Drain, which was also adopted for the reduction of parasitic capacitance due to gate oxide with high dielectric constant. Cutoff frequency (ƒT) increase is moderately obtained with the decrease of gate length. Despite the low gm due to underlap region, we obtained ƒT =80 GHz.

Enhanced Current Drivability of CVD Graphene Interconnect in Oxygen-Deficient Environment

Graphene has been considered as a candidate for interconnect metal due to its high carrier mobility and current drivability. In this letter, the breakdown mechanism of single-layer chemical-vapor-deposited (CVD) graphene and triple-layer CVD graphene has been investigated at three different conditions (air exposed, vacuum, and dielectric capped) to identify a failure mechanism. In vacuum, both single- and triple-layer graphenes demonstrated a breakdown current density as high as ~108 A/cm2, which is similar to that of exfoliated graphene. On the other hand, the breakdown current of graphene exposed to air was degraded by one order of magnitude from that of graphene tested in vacuum. Thus, oxidation initiated at the defect sites of CVD graphene was suggested as a major failure mechanism in air, while Joule heating was more dominant with dielectric capping and in vacuum.