Hyung-Jin Lee

A TDC-less ADPLL with 200-to-3200MHz range and 3mW power dissipation for mobile SoC clocking in 22nm CMOS

Mobile SoC designs demand a low-power clocking system to maximize battery life. The host PLL is critical since it must remain enabled to support always-on, always-connected operation. In addition, the host PLL should offer wide frequency range, low area, flexible bandwidth, scalability to future manufacturing processes, negligible lock time compared to the power-state-cycling time, and acceptable period jitter for clocking digital logic.

A 3 to 5GHz CMOS UWB LNA with input matching using miller effect

A UWB CMOS LNA uses the Miller effect with one additional inductor to achieve a broadband input match. The LNA has a power gain>15dB, S11<-10.5dB, S22< -13.1dB and NF<2.3dB over the 3 to 5GHz range. It is fabricated in 0.18mum CMOS and draws 6.4mA from a 1.8V supply

A 32 nm SoC With Dual Core ATOM Processor and RF WiFi Transceiver

An &times; 86 standard operating system compliant System-on-Chip (SoC) with a dual core ATOM processor and a custom interconnect fabric to enable modular design is presented. The 32 nm SoC includes integrated PCI-e Gen 2, DDR3, legacy I/O, voltage regulators, clock generation, power management, memory controller and RF portion of a WiFi transceiver in a 32 nm high-k/metal-gate RF CMOS process with high resistivity substrate. The integrated RF transceiver for 2.4 GHz 802.11g operation achieves a receive sensitivity of -74 dBm, -8 dBm IIP3 and a transmit output power of 20.3 dBm (-25 dB EVM) at 14% TX RF efficiency.

32nm x86 OS-compliant PC on-chip with dual-core Atom® processor and RF WiFi transceiver

Embedded PC applications are growing, driven by their cost, performance and software compatibility. The SoC described in this work is a unique device designed for rapid integration and customization for specific market segments. A rich multi-source IP eco-system consisting of standardized interfaces, modular and configurable building blocks, enables automation and fast execution to deliver a broad range of targeted solutions. Integrating high-performance digital circuits with analog and RF circuits on a leading edge process enables our SoC architecture to increase the level of integration, performance and reduce the cost of the platform. WiFi has remained an external PC component due to the challenges of managing system noise from the digital circuits. This paper presents an integrated standard x86 OS compliant, dual-core ATOM® processor-based SoC, including the RF WiFi to drive down platform cost. Key enabling features are: (a) a 32nm RF process with HV transistors and RF passives; (b) an on-chip interconnect fabric for modularity; (c) a clock generator with SSC to reduce substrate noise injection and EMI; (d) voltage regulators for power management and rail reduction; (e) an 802.11b/g RF WiFi transceiver with integrated LNA, PA, T/R switch and BIST/calibration engine.

A scalable sub-1.2mW 300MHz-to-1.5GHz host-clock PLL for system-on-chip in 32nm CMOS

System-on-chips (SoCs) are being widely adopted in mobile applications, and are driven by the need for longer battery life, their power budget continues to decrease. In addition, the phase-locked loop (PLL) for the SoC host clock has to be a very low power circuit to support the always-on always-connected (AOAC) feature for SoCs integrated into hand-held devices. The proposed PLL, implemented in a high-k metal-gate 32nm logic CMOS technology, provides process scalability to the next process technology node, uncompromised system response, and loop stability under process variation and minimum power envelop constraints. As the jitter requirements for the host clocking PLL are not stringent, the proposed architecture emphasizes the power efficiency over the jitter performance.