Hyung-Joon Chi

A 3Gb/s 8b single-ended transceiver for 4-drop DRAM interface with digital calibration of equalization skew and offset coefficients

A 3Gbit/s/pin 8b parallel 4-drop single-ended DRAM transceiver is implemented in a 0.25 /spl mu/m CMOS process. Digital calibrations are performed for equalization and compensation of data skew and offset voltage. A continuously active on-die termination is used to reduce reflections. A phase detector is proposed for the digital DLL to achieve the S/H time of 10ps.

Serpentine Microstrip Lines With Zero Far-End Crosstalk for Parallel High-Speed DRAM Interfaces

Serpentine microstrip lines are proposed to eliminate the far-end crosstalk in parallel high-speed interfaces by increasing the capacitive coupling ratio to equal the inductive coupling ratio. Zero far-end crosstalk voltage waveform and zero crosstalk-induced jitter (CIJ) were achieved on an FR4 printed circuit board, by adjusting the unit section length of the serpentine structure. Application of the proposed serpentine microstrip lines to the 2-drop stub series terminated logic DRAM channel increased the maximum data rate from 0.9 to 1.4 Gb/s and reduced CIJ by ~ 78 ps at 3.3 Gb/s.

A VCDL-based 60-760-MHz dual-loop DLL with infinite phase-shift capability and adaptive-bandwidth scheme

A dual-loop delay-locked loop (DLL) was implemented by using an analog voltage-controlled delay line (VCDL) for low jitter. An infinite phase-shift capability with seamless phase change was achieved by adding a look-ahead VCDL. A low jitter was achieved for the entire input frequency lock range from 60 to 760 MHz by using the adaptive bandwidth scheme in both reference and fine loops. A wide input-frequency lock range was achieved due to the combined effects of the dual-loop architecture and the extra phase detector of the reference DLL. The extra phase detector eliminated the constraint on the initial VCDL delay for DLL to be locked. Measurements on the fabricated chip by using a 0.18-/spl mu/m CMOS process showed a power consumption of 63 mW at 700 MHz, an active chip area of 370/spl times/510 /spl mu/m/sup 2/, and peak-to-peak jitters of 28 and 39 ps at the 700-MHz synchronous and plesiochronous operations, respectively.

A 2Gb/s 2-tap DFE receiver for mult-drop single-ended signaling systems with reduced noise

A 2Gb/s integrating 2-tap decision feedback equalizer receiver is implemented in a 0.25/spl mu/m CMOS process to reduce high- and low-frequency noise for multi-drop single-ended signaling system. Voltage margin is enhanced by 110%(90%) for a stubless channel at 2Gb/s (an SSTL channel at 1.2Gb/s).

A 3.2Gb/s 8b Single-Ended Integrating DFE RX for 2-Drop DRAM Interface with Internal Reference Voltage and Digital Calibration

A 3.2Gb/s single-ended current-integrating DFE receiver with 8b parallel data for 2-drop DRAM interface is implemented in a 0.18mum CMOS process. The reference voltage for the receiver is generated internally to reduce the external coupling noise. A single-loop implementation of sign-sign LMS algorithm is used to decide the single-tap equalization coefficient of the DFE receiver instead of the previous dual-loop implementation.

A 2-Gb/s CMOS Integrating Two-Tap DFE Receiver for Four-Drop Single-Ended Signaling

A 2-Gb/s integrating decision-feedback equalization (DFE) receiver was implemented for a four-drop single-ended DRAM interface channel by using a 0.25- mum CMOS process. The receiver combines both DFE and integration operations in a single receiver circuit so that the DFE operation reduces the intersymbol interference and the integration operation reduces the high-frequency noise. The DFE operation was implemented by switching the capacitance values of the two output nodes of a differential integrator, depending on the previous decision data. A look-ahead scheme was used to reduce the DFE loop delay. A MUX-embedded D flip-flop was used in the look-ahead circuit to further reduce the DFE loop delay and latency. The DFE operation enhanced the voltage margins by 110% and 90% at the 2-Gb/s stubless channel and the 1.2-Gb/s stub series terminated logic channel, respectively. The chip area and the power dissipation of the proposed receiver chip were 220 times 120 mum2 and 10 mW, respectively, at the data rate of 2 Gb/s.

6.3: A Low‐EMI 2Gbps ClockAlignedtoData IntraPanel Interface (CADI) for TFT‐LCD with the VSYNC‐Embedded Clock and Equalization

A pointtopoint intrapanel interface for data and clock of TFT LCD in 0.18um works at 2Gbps, with the 10∼20dB EMI enhancement over the clock embedding scheme. The subpixel clock is cascaded with the transition time maximized for low EMI. The VSYNC is embedded in the clock. DLL aligns clock and data.