Hyungwook Kim

Power-Combining Transformer Techniques for Fully-Integrated CMOS Power Amplifiers

Fully integrated CMOS power amplifiers (PAs) with parallel power-combining transformer are presented. For the high power CMOS PA design, two types of transformers, series-combining and parallel-combining, are fully analyzed and compared in detail to show the parasitic resistance and the turn ratio as the limiting factor of power combining. Based on the analysis, two kinds of parallel-combining transformers, a two-primary with a 1:2 turn ratio and a three-primary with a 1:2 turn ratio, are incorporated into the design of fully-integrated CMOS PAs in a standard 0.18-mum CMOS process. The PA with a two-primary transformer delivers 31.2 dBm of output power with 41% of power-added efficiency (PAE), and the PA with a three-primary transformer achieves 32 dBm of output power with 30% of PAE at 1.8 GHz with a 3.3-V power supply.

A Linear Multi-Mode CMOS Power Amplifier With Discrete Resizing and Concurrent Power Combining Structure

Efficiency degradation effects of power combining transformers with partially disabled inputs are quantitatively analyzed. To improve efficiencies in lower-power modes of a multi-mode class-AB power amplifier (PA), a discrete resizing technique is introduced in combination with a parallel-combining transformer (PCT). The two-stage PA implemented in a 0.18-μm CMOS technology also includes varactor-based tunable matching circuits. The design method involves parallel-combining of two power stages, each of which are divided into three sub-cells to facilitate discrete resizing. The parallel-combining of concurrently resized power cells minimizes undesired power loss through the transformer and helps the PA to utilize the transformer efficiency maximally independent of the number of combining cells. When operating in the high-power mode, the PA exhibits a peak output power of 31 dBm with a PAE of 34.8%. Power back-offs are realized by discretely turning off parallel sub-amplifier cells concurrently, achieving output power levels of 26 dBm and 22.3 dBm with respective PAE of 22.5% and 15%. The EVM has been measured with IEEE 802.11g WLAN and 802.16e WiMAX modulated signals in three operation modes. In the high-power mode, the PA dissipates 590 mA from a 3.3 V supply.

A 2.4 GHz Fully Integrated Linear CMOS Power Amplifier With Discrete Power Control

A fully integrated 2.4 GHz CMOS power amplifier (PA) in a standard 0.18 mum CMOS process is presented. Using a parallel-combining transformer (PCT) and gate bias adaptation, a discrete power control of the PA is achieved for enhancing the efficiency at power back-off. With a 3.3 V power supply, the PA has a peak drain efficiency of 33% at 31 dBm peak output power. By applying discrete power control, a reduction of 650 mA in current consumption can be achieved over the low output power range while satisfying the EVM requirements of WLAN 802.11g and WiMAX 802.16e signals.

A Fully-Integrated High-Power Linear CMOS Power Amplifier With a Parallel-Series Combining Transformer

In this paper, a linear CMOS power amplifier (PA) with high output power (34-dBm saturated output power) for high data-rate mobile applications is introduced. The PA incorporates a parallel combination of four differential PA cores to generate high output power with good efficiency and linearity. To implement an efficient on-chip power combiner in a small form-factor, we propose a parallel-series combining transformer (PSCT), which mitigates drawbacks and limitations of conventional power-combining transformers such as a series combining transformer (SCT) and a parallel combining transformer (PCT). Using the proposed PSCT, a two-stage class-AB PA is designed and fabricated in a 0.18-μm CMOS technology. The PA achieves a P1dB of 31.5 dBm , a Psat of 34 dBm, and a Plinear of 23.5 dBm with a peak PAE of 34.9% (peak drain efficiency of 41%) at the operating frequency of 2.4 GHz . A detailed analysis of the proposed PSCT is introduced along with comparisons to the conventional monolithic power-combining transformers. A design methodology of the integrated CMOS PA is also presented.

A Monolithic Voltage-Boosting Parallel-Primary Transformer Structures for Fully Integrated CMOS Power Amplifier Design

In this paper, a novel monolithic voltage-boosting parallel-primary transformer is presented for the fully integrated CMOS power amplifier design. Multiple primary loops are interweaved in parallel to combine the AC currents from multiple power devices while the higher turn ratio of a secondary loop boosts AC voltages of the combined primary loops at the load of the secondary loop. The proposed interweaved structure is much more compact and separable from power devices, avoiding potential instability. To verify the feasibility of this power combining method, the fully integrated CMOS switching power amplifier was implemented in a standard 0.18-mum technology. The power amplifier successfully demonstrated a measured output power of 1.3 W and a measured power added efficiency (PAE) of 41% to a 50-Omega load with a 3.3-V power supply at 1.8 GHz operation.

A 1.8-GHz 2-Watt Fully Integrated CMOS Push-Pull Parallel-Combined Power Amplifier Design

This paper newly presents a push-pull parallel-combined CMOS power amplifier (PA) and its analysis of operation. The proposed class-E CMOS PA incorporates the push-pull parallel-combined power devices with the 1:1:2 (two single-turn primary windings and a two-turn secondary winding) step-up on-chip transformer. The PA is fully integrated in a standard 0.18-mum CMOS technology without any external balun or matching networks. The operation of the PA with a multi-turn on-chip transformer is substantially analyzed in order to optimize the device size and its structure. Experimental data demonstrates the output power of 2-watt and the power-added efficiency (PAE) of more than 30% with a 3.3-V of power supply at 1.8 GHz. This is the new demonstration of the compact fully integrated CMOS PA with 2-watt of output power with very stable operation at 1.8 GHz range.

A High-Power and Highly Linear CMOS Switched Capacitor

A new CMOS switched capacitor is developed to be used for high-power applications such as a power amplifier, where high voltage handling capability and low distortion are two major factors. In order to demonstrate superior performance of the proposed structure over a conventional structure, two designs are analyzed and compared while maintaining comparable small signal characteristics such as a 2:1 tuning ratio and a quality factor. The maximum applicable voltage swing of the proposed structure is improved over the conventional structure by a factor of VDD / Vth, or 12 dB in this design. The proposed structure also shows a greatly improved two-tone third-order inter-modulation distortion characteristic with a maximum 34 dB improvement. This proposed structure is a suitable component for tunable CMOS power amplifier applications.

A 40% PAE linear CMOS power amplifier with feedback bias technique for WCDMA applications

A highly efficient CMOS linear power amplifier for WCDMA applications with feedback bias technique is presented. The method involves connecting the gates of common-gate devices of the driver stage and the power stage in cascode configurations by a feedback network for enhancing linearity. To achieve high efficiency and linearity simultaneously, large-signal IMD minimum (IMD sweet spot) is properly used at the desired output power level. The proposed PA was fabricated in a 0.18-µm CMOS technology. The experimental results demonstrate a gain of 26 dB, a maximum output power of 26 dBm with 46.4% of peak PAE, and a linear output power of 23.5 dBm with 40% PAE using a 3GPP WCDMA modulated signal. Both simulation and measurement results show an excellent large-signal IMD minimum at the output power using a WCDMA modulated signal.

A 0.18/spl mu/m CMOS equalizer with an improved multiplier for 4-PAM/20Gbps throughput over 20 inch FR-4 backplane channels

In this paper, we present a 20 Gbps throughput PAM-4 analog feed forward equalizer with a newly proposed multiplier cell. The conventional Gilbert-cell multiplier is modified to achieve enough voltage headroom for 0.18/spl mu/m standard CMOS process while maintaining high-speed characteristics. Pulse amplitude modulation (PAM)-4 is adopted to increase the overall data throughput over bandwidth limited channel. For the tap delay line implementation, a passive L-C ladder topology is used, which enables fractional symbol tap spacing while maintaining the bandwidth required for 20 Gbps PAM-4 signal. The overall architecture is implemented using 0.18 /spl mu/m, standard CMOS process with 1.8V supply voltage. The 20 Gbps PAM-4 signal is received through the backplane channel, and the signal impairment is successfully compensated through the fabricated FFE.

Fully integrated 0.18/spl mu/m CMOS equalizer with an active inductance peaking delay line for 10Gbps data throughput over 500m multimode fiber

In this paper, we present a fully integrated equalizer for 10Gbps data throughput over multimode fiber. The equalizer uses a newly proposed active delay line approach with an active inductance. The active inductance enables 10Gbps data throughput equalization with an integrated single to differential converter. A buffer stage is also integrated at the output stage to deliver low voltage differential signaling (LVDS) level at the 50-ohm termination. The overall architecture is implemented using a 0.18/spl mu/m, standard CMOS process with a 1.8V supply voltage. The active delay line scheme results in reduced equalizer chip area in comparison to a passive delay line approach. The 10Gbps non return-to-zero (NRZ) signal is received through a 500m multimode fiber channel, and the signal impairment due to the differential mode delay is successfully compensated.