Youngchang Yoon

A Linear Multi-Mode CMOS Power Amplifier With Discrete Resizing and Concurrent Power Combining Structure

Efficiency degradation effects of power combining transformers with partially disabled inputs are quantitatively analyzed. To improve efficiencies in lower-power modes of a multi-mode class-AB power amplifier (PA), a discrete resizing technique is introduced in combination with a parallel-combining transformer (PCT). The two-stage PA implemented in a 0.18-μm CMOS technology also includes varactor-based tunable matching circuits. The design method involves parallel-combining of two power stages, each of which are divided into three sub-cells to facilitate discrete resizing. The parallel-combining of concurrently resized power cells minimizes undesired power loss through the transformer and helps the PA to utilize the transformer efficiency maximally independent of the number of combining cells. When operating in the high-power mode, the PA exhibits a peak output power of 31 dBm with a PAE of 34.8%. Power back-offs are realized by discretely turning off parallel sub-amplifier cells concurrently, achieving output power levels of 26 dBm and 22.3 dBm with respective PAE of 22.5% and 15%. The EVM has been measured with IEEE 802.11g WLAN and 802.16e WiMAX modulated signals in three operation modes. In the high-power mode, the PA dissipates 590 mA from a 3.3 V supply.

A Dual-Mode CMOS RF Power Amplifier With Integrated Tunable Matching Network

A dual-mode CMOS power amplifier (PA) with an integrated tunable matching network is presented. A switched capacitor is fully analyzed to implement a tunable matching network in terms of power-handling capability, tuning ratio, quality factor, and linearity. Based on the presented consideration, a 3.3-V 2.4-GHz fully integrated CMOS dual-mode PA is implemented in a 0.18-μm CMOS process. The PA has two power modes, high-power and low-power (LP), and each mode is optimally matched by the tunable matching network. The LP mode enables more than 50% dc current reduction from 0- to 10-dBm power range. The improved efficiency in this study is approximately twice that of other multimode CMOS PAs reported thus far.

A Fully-Integrated High-Power Linear CMOS Power Amplifier With a Parallel-Series Combining Transformer

In this paper, a linear CMOS power amplifier (PA) with high output power (34-dBm saturated output power) for high data-rate mobile applications is introduced. The PA incorporates a parallel combination of four differential PA cores to generate high output power with good efficiency and linearity. To implement an efficient on-chip power combiner in a small form-factor, we propose a parallel-series combining transformer (PSCT), which mitigates drawbacks and limitations of conventional power-combining transformers such as a series combining transformer (SCT) and a parallel combining transformer (PCT). Using the proposed PSCT, a two-stage class-AB PA is designed and fabricated in a 0.18-μm CMOS technology. The PA achieves a P1dB of 31.5 dBm , a Psat of 34 dBm, and a Plinear of 23.5 dBm with a peak PAE of 34.9% (peak drain efficiency of 41%) at the operating frequency of 2.4 GHz . A detailed analysis of the proposed PSCT is introduced along with comparisons to the conventional monolithic power-combining transformers. A design methodology of the integrated CMOS PA is also presented.

Highly Linear RF CMOS Variable Attenuators With Adaptive Body Biasing

Several approaches to design a linear attenuator have been analyzed in terms of the transistor impedance variation, linearity, frequency responses, and circuit complexity. This paper proposes a novel method of using an adaptive bootstrapped body biasing. The method allows the attenuator to have maximum power handling capability and bandwidth without adding complexity to the circuit. A π-type variable attenuator for WCDMA transmitters has been designed and fabricated using IBM 0.18-μ m triple-well CMOS technology. The attenuator has a linear-in-dB controllability from 400 MHz to 3.7 GHz with an attenuation range of 33 dB. Its insertion loss is 0.9-2.9 dB and worst-case return loss is better than -9 dB within this frequency band. The minimum input 1-dB compression point (IP1dB) is above 7.5 dBm, and the minimum IIP3 is greater than 17 dBm at 1.95 GHz. To our knowledge, this design achieves the best linearity performance and frequency responses, and has the smallest area among similar CMOS works.

An Ultra-Compact, Linearly-Controlled Variable Phase Shifter Designed With a Novel RC Poly-Phase Filter

This paper proposes a new vector-sum type variable-phase shifter (VPS) topology for predistorting the phase of a modulated signal for an analog-predistortion power amplifier system. It has a continuous linear-in-degree control curve over a 90° phase-control range and has the smallest size among all those proposed CMOS works. The phase shifter utilizes an improved RC poly-phase filter to generate in-phase and quadrature-phase vectors. It uses fewer RC components but has a wider phase-splitting bandwidth than traditional RC filters, reducing the loss and size of the overall VPS. Specially-designed control circuits give the shifter a linear phase-control capability, minimizing the gain variation over the phase-control range. The phase shifter, optimized for WCDMA applications, has been fabricated in a standard 0.18-μm CMOS process. The area of the phase shifter core is 0.063 mm2. The measured operation frequency is from 1 to 2.1 GHz, which is an overlap of its 3-dB cutoff frequency and bandwidth of a 90° phase-control range. Within the bandwidth, this phase shifter displays a linear control curve with phase errors of less than ±1° over a 70° tuning range, making it suitable for accurate AM-PM error compensation.

A High-Power and Highly Linear CMOS Switched Capacitor

A new CMOS switched capacitor is developed to be used for high-power applications such as a power amplifier, where high voltage handling capability and low distortion are two major factors. In order to demonstrate superior performance of the proposed structure over a conventional structure, two designs are analyzed and compared while maintaining comparable small signal characteristics such as a 2:1 tuning ratio and a quality factor. The maximum applicable voltage swing of the proposed structure is improved over the conventional structure by a factor of VDD / Vth, or 12 dB in this design. The proposed structure also shows a greatly improved two-tone third-order inter-modulation distortion characteristic with a maximum 34 dB improvement. This proposed structure is a suitable component for tunable CMOS power amplifier applications.

A 40% PAE linear CMOS power amplifier with feedback bias technique for WCDMA applications

A highly efficient CMOS linear power amplifier for WCDMA applications with feedback bias technique is presented. The method involves connecting the gates of common-gate devices of the driver stage and the power stage in cascode configurations by a feedback network for enhancing linearity. To achieve high efficiency and linearity simultaneously, large-signal IMD minimum (IMD sweet spot) is properly used at the desired output power level. The proposed PA was fabricated in a 0.18-µm CMOS technology. The experimental results demonstrate a gain of 26 dB, a maximum output power of 26 dBm with 46.4% of peak PAE, and a linear output power of 23.5 dBm with 40% PAE using a 3GPP WCDMA modulated signal. Both simulation and measurement results show an excellent large-signal IMD minimum at the output power using a WCDMA modulated signal.

A discrete resizing and concurrent power combining structure for linear CMOS power amplifier

We propose a new method of power combining for a parallel-combining-transformer (PCT)-based CMOS linear power amplifier (PA). The power cell in parallel paths is divided into three sub-cells to implement device resizing for discrete power control. Concurrent power combining of sub-power-cells utilizes the maximum available transformer efficiency even at the low-power mode, boosting overall PA efficiency. When all sub-power-cells are enabled, the PA exploits output power of 30.7 dBm with PAE of 35.8%. Power back-offs of 6 dB and 12 dB are achieved by discretely turning off sub-cells, showing output power of 25 dBm and 19 dBm with PAE of 19.8% and 10.5%, respectively. With 802.11g WLAN modulated signal used for linearity test, the PA shows 21-dBm output power satisfying −25-dB EVM requirements consuming 560 mA from 3.3 V power supply.

A fully integrated CMOS RF power amplifier with tunable matching network for GSM/EDGE dual-mode application

A fully integrated power amplifier operating at switching and linear mode is implemented using 0.18-µm CMOS technology. To maximize performance for both operation modes, the fundamental load impedances are optimized with a variable capacitor for GSM and EDGE application. For GSM application, 32 dBm of the output power with 45 % of the drain efficiency is achieved at 1.76 GHz. With EDGE modulation signal at 1.76 GHz, error vector magnitude (EVM) has an RMS value of less than 5 % up to 27.5 dBm of the output power, and 28.1 % of modulated PAE is achieved at this power. The output spectrum is confined within the inside of mask up to 27.5 dBm of the output power.

A linearity improvement technique for a class-AB CMOS Power Amplifier with a direct feedback path

A new linearity improvement technique is introduced for a class-AB CMOS Power Amplifier (PA). The proposed PA has two stages and each stage has a cascode configuration. A direct feedback path from the input of the power stage to the input of the driver stage via an Accumulation-mode MOS (AMOS) varactor is adopted to improve the linearity. This additional path provides a negative feedback loop for the second-order harmonic, and the AMOS varactor controls the loop gain and the amount of the phase shift of the feedback signals. The proposed PA has been implemented in a standard 0.18-μm CMOS technology. The measured results show a gain of 21.4 dB, a maximum output power of 23.5 dBm with 43.1 % of peak Power-Added-Efficiency (PAE), and a linear output power of 21.4 dBm with 40 % PAE using a 1.85 GHz single tone. The two-tone test demonstrates 10 dBc improvement in the third-order Intermodulation Distortion (IMD3) compared to a conventional PA.Q