Edward Gebara

Analysis and design of an interference canceller for collocated radios

An active interference cancellation scheme is presented to mitigate interference between Bluetooth and wireless local area network (IEEE 802.11 b) radios operating in close proximity. This method is extensible to other mutually interfering radio devices. A reference signal correlated to the original interferer is used to generate a cancellation signal by means of amplitude and phase alignment, and filtration. The filter employed emulates the coupling channel responsible for interference. An implementation of this procedure in 0.18-/spl mu/m Si-complementary metal-oxide-semiconductor (CMOS) integrated-circuit (IC) technology is also presented. The circuits fabricated are tunable and are controlled by a closed-loop adaptive process including an error minimization method. The cancellation system designed achieves 15-30 dB of interference suppression for different cases. A total power of 14 mW is dissipated by the CMOS ICs designed.

A 5.8 GHz fully integrated low power low phase noise CMOS LC VCO for WLAN applications

A fully integrated low power and low phase noise 5.8 GHz VCO is designed and fabricated in standard 0.24 /spl mu/m single-poly, 5-metal digital CMOS process. The VCO-core draws 2 mA of current from a 2.5 V supply. Measured phase noise at 1 MHz offset from the center frequency is -112 dBc/Hz. It has a tuning range of 810 MHz with low phase noise performance throughout the tuning range. It meets the requirements for IEEE802.11a WLAN standard. Low power and low phase noise have been achieved simultaneously by the use of np complementary cross-coupled topology. The novel orientation of the inductor pair used in the design minimizes the effect of any unwanted common-mode magnetic coupling that may arise from other on-chip inductors in an integrated environment.

Study of self-heating effects, temperature-dependent modeling, and pulsed load-pull measurements on GaN HEMTs

On-wafer RF and IV characterizations are performed for the first time on power GaN high electron-mobility transistors (HEMTs) under pulse and continuous conditions at different temperatures. These measurements give an in-depth understanding of self-heating effects and allow one to investigate the possibility of improving heat-dissipation mechanisms. A pulsed load-pull system that measures the power gain of the device-under-test (DUT) under pulsed RF and bias condition has been developed. To the best of our knowledge, this is the first time that the reflected power at the DUT is measured under the pulse mode of operation. Additionally, an improved small-signal model for power GaN HEMTs that incorporates the geometry of the device is developed at various temperatures. This is the basis for empirical large-signal modeling.

Realization of multigigabit channel equalization and crosstalk cancellation integrated circuits

In this paper, we present integrated circuit solutions that enable high-speed data transmission over legacy systems such as short reach optics and electrical backplanes. These circuits compensate for the most critical signal impairments, intersymbol interference and crosstalk. The finite impulse response (FIR) filter is the cornerstone of our architecture, and in this study we present 5- and 10-Gsym/s FIR filters in 2-/spl mu/m GaAs HBTs and 0.18-/spl mu/m CMOS, respectively. The GaAs FIR filter is used in conjunction with spectrally efficient four-level pulse-amplitude modulation to demonstrate 10-Gb/s data throughput over 150 m of 500 MHz/spl middot/km multimode fiber. The same filter is also used to demonstrate equalization and crosstalk cancellation at 5 Gb/s on legacy backplane. The crosstalk canceller improves the bit error rate by five orders of magnitude. Furthermore, our CMOS FIR filter is tested and demonstrates backplane channel equalization at 10 Gb/s. Finally, building blocks for crosstalk cancellation at 10 Gb/s are implemented in a 0.18-/spl mu/m CMOS process. These circuits will enable 10-Gb/s data rates on legacy systems.

Equalization and near-end crosstalk (NEXT) noise cancellation for 20-Gb/s 4-PAM backplane serial I/O interconnections

Limitations in current backplane environments impede high-speed data transmission above 5 Gb/s. A system architecture to extend the transmission capacities of legacy backplanes is proposed. The incentives for using a four-level pulse amplitude modulation (4-PAM) scheme are also presented. The architecture is built from feed-forward equalizer and tunable filter elements for near-end crosstalk noise cancellation. Each of the circuits is implemented in a standard 0.18-/spl mu/m CMOS process. The building blocks of the architecture, which include an LC ladder, a modified Gilbert-cell multiplier with improved headroom, and a tunable active high-pass filter are described in detail. Results of the architecture are shown demonstrating 20-Gb/s 4-PAM signal transmission.

A highly integrated transceiver module for 5.8 GHz OFDM communication system using multi-layer packaging technology

A highly integrated transceiver module for 5.8 GHz OFDM communication system is presented. The antenna and filter are directly fabricated on the module using multi-layer packaging technology in order to reduce size and interconnection losses. A cavity backed patch antenna with a vertical feed and an embedded 3D filter have been designed and integrated on the package using a low-temperature cofired ceramic (LTCC) process. RF functional blocks including PA, LNA, mixers and VCO are developed using GaAs-based MMICs and are attached on the surface of the LTCC board. RF blocks are vertically stacked and connected through via structures. The specifications of the functional blocks have been determined and verified through system simulations based on the IEEE 802.11a standard. The total size of the module is 14/spl times/19/spl times/2 mm/sup 3/. Measurement and simulation results of the components and the module are also presented.

Thermal analysis of AlGaN-GaN power HFETs

In this paper, we present a thermal analysis of AlGaN-GaN power heterojunction field-effect transistors (HFETs). We report the dc, small-signal, large-signal, and noise performances of AlGaN-GaN HFETs at high temperatures. The temperature coefficients measured for GaN HFETs are lower than that of GaAs pseudomorphic high electron-mobility transistors, confirming the potential of GaN for high-temperature applications. In addition, the impact of thermal effects on the device dc, small-signal, and large-signal characteristics is quantified using a set of pulsed and continuous wave measurement setups. Finally, a thermal model of a GaN field-effect transistor is implemented to determine design rules to optimize the heat flow and overcome self-heating. Arguments from a device, circuit, and packaging perspective are presented.

RF Fingerprinting Physical Objects for Anticounterfeiting Applications

Rendering typical RF identification (RFID) tags physically unique and hard to near-exactly replicate by complementing them with unique RF certificates of authenticity (RF-CoAs) can prove a valuable tool against counterfeiting. This paper introduces a new robust RFID system with enhanced hardware-enabled authentication and anticounterfeiting capabilities that relies on the near-field RF effects between a 5 × 5 antenna array and the uniquely modified substrate of the RF-CoAs. A microcontroller-enabled, low-power, and low-cost reader is used to accurately extract the near-field response (“RF fingerprint”) of the certificates meant to complement typical RFID tags in the 5-6-GHz frequency range. The RF characterization of all the readers components, with an emphasis on the accuracy provided, has been performed. The state diagram of the fast and accurate reader operation is outlined. Rigorous performance and security test results are presented and verify the unique features of this technology.

0.18-/spl mu/m CMOS equalization techniques for 10-Gb/s fiber optical communication links

Limitations in data transmission caused by modal dispersion in fiber-optic links can be significantly improved using equalization techniques. In this paper, two different equalizer implementation approaches are proposed to extend the transmission capacities of existing fiber-optic links. The building blocks of the equalizer including a multiplier cell, a delay line, and an output buffer stage are fully integrated on a 0.18-/spl mu/m CMOS process. For the continuous-time tap-delay implementation, a passive LC delay line and an active inductance peaking delay line are compared for performance against process variation, as well as power consumption. In addition, a delay-locked loop is proposed to counter delay variations caused by changes in the process corner. A 10-Gb/s nonreturn-to-zero signal is received after transmission through a 500-m multimode-fiber channel, and the signal impairment due to the differential modal delay is successfully compensated using both feed-forward equalizers.

High-frequency noise in AlGaN/GaN HFETs

We present in this letter the benefits of GaN-based electronic devices for low-noise MMICs. A temperature-dependent two-temperature noise model for AlGaN/GaN HFETs is implemented on a wide range of bias conditions. This study enables to access the device high-frequency noise parameters, and allow a comparison of the noise performances with SiC and GaAs technologies.