Ian D. Melville

Chip Package Interaction for 65nm CMOS Technology with C4 Interconnections

This paper discusses the chip package interaction (CPI) for a 65 nm low k BEOL CMOS chip assembled to an organic package. Inter-level dielectrics with k~3.0 and k~2.7, with oxide terminations, were used in combination with both Sn/Pb and lead-free C4s. Various underfill compounds were tested to determine their effectiveness in mitigating chip stresses without significantly impairing C4 fatigue life. A summary of the reliability stress results will be presented.

End-to-End Integration of a Multi-die Glass Interposer for System Scaling Applications

The processes key to enabling 3D manufacturing, namely, bond, backgrind, and through silicon via (TSV) reveal, are extended for 300 mm glass substrates to fabricate a heterogeneous, multi-die, 2.5D glass interposer. Based on an existing silicon interposer offering, the glass interposer is comprised of multi-level “device” side copper wiring, with line space (L/S) of ≤ 2.5 μm, built using damascene techniques, a 55 μm glass core with through glass vias (TGVs), and multiple UBM levels finished with tin silver (SnAg) C4 bumps. The 300mm TGV wafers are processed on existing silicon wafer manufacturing equipment following established, integrated silicon process flows. Once fully processed, the glass wafers are diced, and the interposer joined to a ceramic carrier by mass reflow. Sub-assemblies are then underfilled, the top die attached, and lidding completed. The final assemblies are tested to evaluate performance of chip to chip interconnects, chip-to-package (through interposer) interconnects, and chip-to-PCB (through interposer and package) interconnects. Results of loss vs frequency measurements are compared, for the glass interposer against the existing silicon interposer results.

BEOL lithography for early development at the 65-nm node

This paper will present results obtained during the early development of a lithography process to meet the requirements of the 65 nm node in the BEOL. For the metal levels, an IBM/JSR jointly developed trench level resist was characterized and implemented. Resist image profile, process window, through pitch performance, image shortening and the effect of illumination conditions are discussed. Results from focus - exposure monitor (FEM) wafers are shown which were characterized for minimum resolution, process window and electrical continuity through a maze structure. For the via levels, results from another IBM/JSR jointly developed resist with high resolution and process windows are described. Process windows for nested and isolated vias are given, as well as results showing the improvement in process window and resolution due to the ARC etch. The results also include FEM measurements showing the electrical continuity through simple via chain structures versus the dimension of the via.