Matthew Angyal

Electromigration-resistance enhancement with CoWP or CuMn for advanced Cu interconnects

Suppressing Cu diffusion along the Cu/Cap interface has proven to be one of the most effective ways to enhance the electromigration (EM) resistance of advanced Cu interconnects. Two methods, depositing a thin layer of CoWP on the Cu surface and doping the Cu seed layer with Mn, are presented in this paper. While each effectively enhanced the EM performance, they behaved somewhat differently in improving the line-depletion and via-depletion EM performance. CoWP functioned primarily as a Cu surface modifier and did not alter the Cu diffusion behavior below the surface, making Cu interconnects capped with CoWP very sensitive to defects in the via. As a result, the hardware processed with CoWP had greatly increased EM failure times, but also had large variability in failure times and activation energy. On the other hand, the hardware with the CuMn seed layer relied on Mn segregation to the Cu surface to slow down the Cu diffusion, plus Mn also may have diffused to grain boundaries and defective areas of the liner. Although the EM failure times of Cu interconnects with CuMn seed in some cases were not as long as those with CoWP, the variability and sensitivity to process defects was reduced.

Critical ultra low-k TDDB reliability issues for advanced CMOS technologies

During technology development, the study of ultra low-k (ULK) TDDB is important for assuring robust reliability. As the technology advances, several critical ULK TDDB issues were faced for the first time and needed to be addressed. First, the increase of ULK leakage current noise level induced by soft breakdown during stress was observed. Second, it was found that ULK had lower field acceleration than dense low-k. Such process and material dependences of ULK TDDB kinetics were investigated, and an optimal process to improve ULK voltage acceleration was identified. Last, as the reliability margin for ULK TDDB of via-related structures is greatly reduced at advanced CMOS technologies, a systematic study of via TDDB regarding area scaling and test structure design was conducted. It was found that only a portion of the total vias possibly determines the low-k via TDDB. A new “fatal” via ratio concept is introduced to replace the as-designed area ratio for TDDB area scaling in structures with vias, and a methodology called shift and compare (S&C) is proposed to determine the “fatal” via ratio.

An enhanced thermo-compression bonding process to address warpage in 3D integration of large die on organic substrates

In this work, a controlled thermo-compression (TC) bonding process has been developed to address problems caused by interposer and laminate warpage when assembling large three-dimensional (3D) integrated circuit (IC) die on an organic substrate (laminate). By using TC bonding, a thin interposer with through-silicon-vias (TSV) is joined to a top die while being held flat by vacuum and vertical pressure. A vacuum distribution plate is developed and used to mitigate warpage during 3D assembly. A unique set of process parameters has been developed which enables the joining of severely bowed, large area interposers to a semiconductor die without C4 (Controlled Collapse Chip Connection) shorting. The controlled TC bonding method developed in this work offers a huge advantage when joining multiple large warped die in a stack. This evaluation used a large 22 nm CMOS top die with ultra low-K (ULK) back end of the line (BEOL) and copper pillar/SnAg solder bumps at two different pitch sizes, 61 μm and 131 μm. Both the top die and interposer die were larger than 600 mm2 while the organic substrate was 68.5 mm × 68.5 mm. The top die and interposer were bonded with parameters developed for an enhanced TC bonding process. Cross-sectional analysis of the 3D assembly showed that the solder joints along the perimeter of chips exhibited good joining with good solder wettability and no solder bridging. Non-destructive X-ray analysis also confirmed that there were no C4 bump bridging across the entire chip area. The experimental results verified that the enhanced TC bonding process can effectively prevent C4 bump bridging and C4 bump electrical opens for a large die packaged in a 3D configuration with a highly warped large area silicon interposer.

Enabling Scatterometry as an In-Line Measurement Technique for 32 nm BEOL Application

Conventional metrology tools are unable to precisely monitor some interconnect attributes such as trench sidewall angle either due to limited capability or excessive cycle time. But these attributes have great impact on interconnect performance for 32 nm technology node and beyond. Scatterometry, a non-destructive metrology technique, is proposed to address the shortcomings of current metrology tools while also potentially providing additional measurement capabilities that enable more comprehensive characterization of interconnect attributes. Enabling scatterometry for back-end-of-line metrology at 32 nm technology node is challenged by the inherent complexity of a multilayer film structure. The research reported describes the implementation of scatterometry measurements to explore the advantages of this technique for the 32 nm technology node. The results obtained demonstrate the superiority of scatterometry techniques over conventional semiconductor metrology tools such as throughput, process control capability, precision, and accuracy. The total measurement uncertainty of scatterometry results with tunneling electron microscope and cross-sectional scanning electron microscope results for line height shows 1.92 and 6.46 nm, respectively, which compare favorably to the reference metrology tools. Scatterometry techniques also exhibited impressive potential to estimate end-of-the-line electrical parametric data. Finally, physical dimensions obtained from scatterometry measurements are shown to be comparable to TEM results from product wafers.

Reliability Challenges in Copper Metallizations arising with the PVD Resputter Liner Engineering for 65nm and Beyond

In this paper the influence of liner deposition parameters on the reliability of 65nm copper metallizations have been investigated for two different deposition sequences. The use of resputter liners in the 65nm generation turned out to change the via-voiding failure mode qualitatively from voiding at the very via-bottom to void nucleation at mid-half of the via. In addition, the resputter intensity and liner thickness have a quantitative impact on the electromigration (EM) failure times and stress migration (SM) failure rates. For a given liner thickness an increasing resputter intensity turned out to improve the overall reliability as a result of a more pronounced anchoring of the via within the metal line underneath. In terms of the liner thickness, thinner barriers yield in general reduced failure times. However, this loss can be compensated at least partially by adjusting the resputter intensity with repsect to the specific liner thickness

Bonding technologies for chip level and wafer level 3D integration

This paper provides a comparison of bonding process technologies for chip and wafer level 3D integration (3Di). We discuss bonding methods and comparison of the reflow furnace, thermo-compression, Cavity ALignment Method (CALM) for chip level bonding, and oxide bonding for 300 mm wafer level 3Di. For chip 3Di, challenges related to maintaining thin die and laminate co-planarity were overcome. Stacking of large thin Si die with 22 nm CMOS devices was achieved. The size of the die was more than 600 mm2. Also, 300 mm 3Di wafer stacking with 45 nm CMOS devices was demonstrated. Wafers thinned to 10 μm with Cu through-silicon-via (TSV) interconnections were formed after bonding to another device wafer. In either chip or wafer level 3Di, testing results show no loss of integrity due to the bonding technologies.

BEOL process integration with Cu/SiCOH (k=2.8) low-k interconnects at 65 nm groundrules

This paper describes a comprehensive characterization of a 65 nm, 300 mm wafer size interconnect technology with SiCOH material (k=2.8). Excellent film properties of the SiCOH material and precise process optimization enable the minimization of layer damage during etching and strip processes. 3D modeling reveals that the k-value of the SiCOH material was maintained at its initial value after the integration. Electrical yield, reliability and chip-to-package (CPI) evaluation are also presented. The results were comparable with the conventional SiCOH integration scheme.

Geometry, kinetics, and short length effects of electromigration in Mn doped Cu interconnects at the 32nm technology node

Mn doping in Cu seed has been used to improve EM performance at the 32nm technology node. This paper will show that on an optimized process with CuMn there were different degrees of EM enhancement for geometric variations including line width and electron flow direction. In addition, kinetics experiments on several geometries resulted in activation energies in the range of 0.95-1.33eV. Finally, the Blech threshold (jL)c=338mA/um was derived from the experimental data on various line lengths and current densities.

Characterization of 32nm Node BEOL Grating Structures Using Scatterometry

Implementations of scatterometry in the back end of the line (BEOL) of the devices requires design of advanced measurement targets with attention to CMP ground rule constraints as well as model simplicity details. In this paper we outline basic design rules for scatterometry back end targets by stacking and staggering measurement pads to reduce metal pattern density in the horizontal plane of the device and to avoid progressive dishing problems along the vertical direction. Furthermore, important characteristics of the copper shapes in terms of their opaqueness and uniformity are discussed. It is shown that the M1 copper thicknesses larger than 100 nm are more than sufficient for accurate back end scatterometry implementations eliminating the need for modeling of contributions from the buried layers. AFM and ellipsometry line scans also show that the copper pads are sufficiently uniform with a sweet spot area of around 20 μm. Hence, accurate scatterometry can be done with negligible edge and/or dishing contributions if the measurement spot is placed any where within the sweet spot area. Reference metrology utilizing CD-SEM and CD-AFM techniques prove accuracy of the optical solutions for the develop inspect and final inspect grating structures. The total measurement uncertainty (TMU) values for the process of record line width are of the order of 0.77 nm and 0.35 nm at the develop inspect and final inspect levels, respectively.

Via-depletion electromigration in copper interconnects

Via-depletion electromigration was studied under a number of conditions in a 65-nm technology. Observed failure distributions were either single mode or bimodal, depending on the structural configuration. The distribution and the time to fail for the early-fail mode of the bimodal distributions varied with linewidth, via redundancy, and via current density. Additionally, it was observed that for bimodal failure distributions, the length of the extension of the line past the via determined the fraction of early fails in the via. The bimodal behavior was suppressed by optimization of the via liner deposition process