Ian M. Mcmackin

Step and Repeat UV nanoimprint lithography tools and processes

Step and FlashTM Imprint Lithography (S-FILTM) process is a step and repeat nano-replication technique based on UV curable low viscosity liquids. Molecular Imprints, Inc. (MII) develops commercial tools that practice the S-FIL process. The current status of the S-FIL tool and process technology is presented in this paper. The specific topics that are covered include: • Residual layer control • Etch process development • Patterning of lines, contacts and posts • CD control • Defect and process life • Alignment and magnification control

Development of imprint materials for the Step and Flash Imprint Lithography process

The Step and Flash Imprint Lithography (S-FILTM) process is a step and repeat nano-replication technique based on UV curable low viscosity liquids. Molecular Imprints, Inc. (MII) develops commercial tools that practice the S-FIL process. This talk will present the imprint materials that have been developed to specifically address the issue of process life and defects. The S-FIL process involves field-to-field dispensing of low viscosity (<5 cps) UV cross-linkable monomer mixtures. The low viscosity liquid leads to important advantages that include: • Insensitivity to pattern density variations • Improved template life due to a lubricated template-wafer interface avoids “hard contact” between template and wafer • Possibility for lubricated (in-situ) high-resolution alignment corrections prior to UV exposure The materials that are optimal for use in the S-FIL process need to possess optimal wetting characteristics, low evaporation, no phase separation, excellent polymer mechanical properties to avoid cohesive failure in the cured material, low adhesion to the template, and high adhesion to the underlying substrate. Over 300 formulations of acrylate based monomer mixtures were developed and studied. The imprint materials were deemed satisfactory based on the process of surviving imprinting more than 1500 imprints without the imprints developing systematic or repeating defects. For the purpose of these process studies, printing of sub-100 nm pillars and contacts is used since they represent the two extreme cases of patterning challenge: pillars are most likely to lead to cohesive failure in the material; and contacts are most likely to lead to mechanical failure of the template structures.

Design and performance of a step and repeat imprinting machine

Molecular Imprints, Inc. (MII) has developed the ImprioTM 100, which is the first commercial step and repeat imprint lithography system with field-to-field alignment. This system is designed to implement the UV curable nano-replication capability of the Step and FlashTM Imprint Lithography (S-FILTM) process. To-date, the Imprio 100 system has demonstrated: 1) Full 200 mm wafer coverage with lithographically useful patterning; 2) Full wafer residual thickness control to enable practical etching (thickness variation < 50 nm, 3 sigma); 3) Field edge control compatible with 50 um kerf regions. 4) Multi-day CD uniformity measured on an analytical SEM < 2 nm, 3 sigma with no process adjustments; 5) Etch pattern transfer including break-through etch of residual material, followed by a bi-layer etch through thick planarization layers; 6) Initial level-to-level alignment target acquisition with accuracy of better than 100 nm. 7) Low air borne particle counts in tool microenvironment consistent with Class 0.1 while imprinting.

Analysis of critical dimension uniformity for Step and Flash imprint lithography

Step and Flash Imprint Lithography (SFIL) is one of several new nano-imprint techniques being actively developed. While SFIL has been shown to be capable of sub-30 nm resolution, critical dimension (CD) control of imprinted features must be demonstrated if SFIL Is to become a viable and production worthy lithography technique. In the current study, a Molecular Imprints Imprio-100 system was used to imprint resolution patterns on 200 mm wafers. A characterization of critical dimension uniformity over the all-quartz template was done and compared to the same features printed on wafers. This analysis was performed for 100, 80, 50, and 30 nm features in three ways: over a single die using 64 sites arrayed across a 21 mm field, from field-to-field for 37 die across a single wafer, and from wafter-to-wafer for six wafers. Results show that CDs transfer from template to wafer with a slight positive bias which is greatest for 50 and 30 nm line sizes. Feature profiles studies. Despite this, the maximum calculated component of process variation from the SFIL process itself was calculated to be only 6 nm.

Direct to digital holography for semiconductor wafer defect detection and review

A method for recording true holograms directly to a digital video medium in a single image has been invented. This technology makes the amplitude and phase for every pixel of the target object wave available. Since phase is proportional wavelength, this makes high-resolution metrology an implicit part of the holographic recording. Measurements of phase can be made to one hundredth or even one thousandth of a wavelength, so the technology is attractive for dining defects on semiconductor wafers, where feature sizes are now smaller than the wavelength of even deep UV light.

High Resolution Defect Inspection of Step and Flash Imprint Lithography for 32 nm Half-Pitch Patterning

Imprint lithography has been shown to be an effective method for the replication of nanometer-scale structures from an imprint mask (template) or mold. Step and Flash Imprint Lithography (S-FIL®) is unique in its ability to address both resolution and alignment. Recently overlay across a 200 mm wafer of less than 20nm, 3σ has been demonstrated. Current S-FIL resolution and alignment performance motivates the consideration of nano-imprint lithography as a Next Generation Lithography (NGL) solution for IC production. During the S-FIL process, a transferable image, an imprint, is produced by mechanically molding a liquid UV-curable resist on a wafer. Acceptance of imprint lithography for CMOS manufacturing will require demonstration that it can attain defect levels commensurate with the requirements of cost-effective device production. This report summarizes the result of defect inspections of wafers patterned using S-FIL. Wafer inspections were performed with KLA Tencor- 2132 (KT-2132) and KLA Tencor eS23 (KT-eS32) automated patterned wafer inspection tools. Imprint specific defectivity was shown to be ≤3 cm-2 with some wafers having defectivity of less than 1 cm-2 and many fields having 0 imprint specific defects, as measured with the KT-2132. KT eS32 inspection of 32 nm half pitch features indicated that the random defectivity resulting from the imprint process was low.

Defect inspection for imprint lithography using a die to database electron beam verification system

Imprint lithography has been included on the ITRS Lithography Roadmap at the 32 and 22 nm nodes. Step and Flash Imprint Lithography (S-FILTM) is a unique method for printing sub-100nm geometries. Relative to other imprinting processes S-FIL has the advantage that the template is transparent, thereby facilitating conventional overlay techniques. Further, S-FIL provides sub-100nm feature resolution without the significant expense of multielement, high quality projection optics or advanced illumination sources. However, since the technology is 1X, it is critical to address the infrastructure associated with the fabrication of templates. With respect to inspection, although defects as small as 70nm have been detected using optical techniques, it is clear that it will be necessary to take advantage of the resolution capabilities of electron beam inspection techniques. This paper reports the first systematic study of die-to-database electron beam inspection of patterns that were imprinted using an Imprio 250 system. The die-to-database inspection of the wafers was performed on an NGR2100 inspection system. Ultimately, the most desirable solution is to directly inspect the fused silica template. This paper also reports the results on the first initial experiments of direct inspection fused silica substrates at data rates of 200 MHz. Three different experiments were performed. In the first study, large (350-400nm) Metal 1 and contact features were imprinted and inspected as described above. Using a 12 nm pixel address grid, 24 nm defects were readily detected. The second experiment examined imprinted Metal 1 and Logic patterns with dimensions as small as 70nm. Using a pixel address of 3nm, and a defect threshold of 20 nm, a systematic study of the patterned arrays identified problem areas in the design of the pattern layout. Finally, initial inspection of 200mm fused silica patterned substrates has established proof of concept for direct inspection of imprint templates.

Automated imprint mask cleaning for step-and-flash imprint lithography

Step-and-Flash Imprint Lithography (S-FIL) is a promising lithography strategy for semiconductor manufacturing at device nodes below 32nm. The S-FIL 1:1 pattern transfer technology utilizes a field-by-field ink jet dispense of a low viscosity liquid resist to fill the relief pattern of the device layer etched into the glass mask. Compared to other sub 40nm CD lithography methods, the resulting high resolution, high throughput through clustering, 3D patterning capability, low process complexity, and low cost of ownership (CoO) of S-FIL makes it a widely accepted technology for patterned media as well as a promising mainstream option for future CMOS applications. Preservation of mask cleanliness is essential to avoid risk of repeated printing of defects. The development of mask cleaning processes capable of removing particles adhered to the mask surface without damaging the mask is critical to meet high volume manufacturing requirements. In this paper we have presented various methods of residual (cross-linked) resist removal and final imprint mask cleaning demonstrated on the HamaTech MaskTrack automated mask cleaning system. Conventional and non-conventional (acid free) methods of particle removal have been compared and the effect of mask cleaning on pattern damage and CD integrity is also studied.

Cleaning of step-and-flash imprint masks with damage-free nonacid technology

Step-and-flash imprint lithography S-FIL ® is a promising li- thography strategy for semiconductor manufacturing at device nodes be- low 32 nm. The S-FIL 1:1 pattern transfer technology utilizes a field-by- field ink jet dispense of a low-viscosity liquid resist to fill the relief pattern of the device layer etched into the glass mask. Compared to other sub-40-nm critical dimension CD lithography methods, the resulting high resolution, high throughput through clustering, 3-D patterning capa- bility, low process complexity, and low cost of ownership of S-FIL makes it a widely accepted technology for patterned media as well as a prom- ising mainstream option for future CMOS applications. Preservation of mask cleanliness is essential to avoid the risk of repeated printing of defects. The development of mask cleaning processes capable of re- moving particles adhered to the mask surface without damaging the mask is critical to meet high-volume manufacturing requirements. We present various methods of residual cross-linked resist removal and final imprint mask cleaning. Conventional and nonconventional acid- free methods of particle removal are compared and the effect of mask cleaning on pattern damage and CD integrity is also studied.

A study of imprint-specific defects in the step and flash imprint lithography process

Researchers have demonstrated that imprint lithography techniques have remarkable replication resolution and can pattern sub-5nm structures. However, a fully capable lithography approach needs to address several challenges in order to be useful in manufacturing. For successful manufacturing insertion of Step and Flash Imprint Lithography (S-FILTM) into a broad set of applications such as photonics, magnetic storage, and integrated circuits (ICs), the following practical process related challenges need to be addressed: (i) Printing sub-50nm structures with non-uniform pattern densities: (ii) Precise alignment and overlay with the ability to mix-and-match with photolithography; (iii) Availability of 1X templates; (iv) Achieving appropriate throughput for acceptable cost of ownership; and (v) Minimizing template and imprint process-induced defects to allow acceptable process yields. The last challenge - the ability to achieve low defect densities - is desirable for all applications. However, it is one of the biggest challenges for S-FIL to be accepted in IC fabrication. This article specifically focuses on this last challenge and presents the current status of defect reduction in S-FIL technology. The article starts out by providing a brief background of S-FIL technology, and by including a discussion of the overall status of S-FIL technology in Section 1. Next, an overview of the experiments performed including the defect inspection approaches used is provided in Section 2. Section 3 introduces the classes of defects that are relevant to the S-FIL process. It also provides recent defect data for each of these classes. Section 4 presents defect data gathered over the last three years and provides defect reduction trends over this period. Section 5 discusses the topic of template lifetime. Finally Section 6 provides some concluding remarks. The defect data presented here is based on a large number of short-loop experiments based on optical inspection of templates and wafers; these data are complemented by a modest number of high resolution e-beam inspections to provide insight into S-FIL specific defects at leading edge line widths.