Ecron Thompson

Step and Repeat UV nanoimprint lithography tools and processes

Step and FlashTM Imprint Lithography (S-FILTM) process is a step and repeat nano-replication technique based on UV curable low viscosity liquids. Molecular Imprints, Inc. (MII) develops commercial tools that practice the S-FIL process. The current status of the S-FIL tool and process technology is presented in this paper. The specific topics that are covered include: • Residual layer control • Etch process development • Patterning of lines, contacts and posts • CD control • Defect and process life • Alignment and magnification control

Development of imprint materials for the Step and Flash Imprint Lithography process

The Step and Flash Imprint Lithography (S-FILTM) process is a step and repeat nano-replication technique based on UV curable low viscosity liquids. Molecular Imprints, Inc. (MII) develops commercial tools that practice the S-FIL process. This talk will present the imprint materials that have been developed to specifically address the issue of process life and defects. The S-FIL process involves field-to-field dispensing of low viscosity (<5 cps) UV cross-linkable monomer mixtures. The low viscosity liquid leads to important advantages that include: • Insensitivity to pattern density variations • Improved template life due to a lubricated template-wafer interface avoids “hard contact” between template and wafer • Possibility for lubricated (in-situ) high-resolution alignment corrections prior to UV exposure The materials that are optimal for use in the S-FIL process need to possess optimal wetting characteristics, low evaporation, no phase separation, excellent polymer mechanical properties to avoid cohesive failure in the cured material, low adhesion to the template, and high adhesion to the underlying substrate. Over 300 formulations of acrylate based monomer mixtures were developed and studied. The imprint materials were deemed satisfactory based on the process of surviving imprinting more than 1500 imprints without the imprints developing systematic or repeating defects. For the purpose of these process studies, printing of sub-100 nm pillars and contacts is used since they represent the two extreme cases of patterning challenge: pillars are most likely to lead to cohesive failure in the material; and contacts are most likely to lead to mechanical failure of the template structures.

Direct Imprinting of Dielectric Materials for Dual Damascene Processing

Advanced microprocessors require several (eight or more) levels of wiring to carry signal and power from transistor to transistor and to the outside world. Each wiring level must make connection to the levels above and below it through via/contact layers. The dual damascene approach to fabricating these interconnected structures creates a wiring level and a via level simultaneously, thereby reducing the total number of processing steps. However, the dual damascene strategy (of which there are several variations) still requires around twenty process steps per wiring layer. In this work, an approach to damascene processing that is based on step-and-flash imprint lithography (SFIL) is discussed. This imprint damascene process requires fewer than half as many steps as the standard photolithographic dual damascene approach. By using an imprint template with two levels of patterning, a single imprint lithography step can replace two photolithography steps. Further efficiencies are possible if the imprint resist material is itself a functional dielectric material. This work is a demonstration of the compatibility of imprint lithography (specifically SFIL) with back-end-of-line processing using a dual damascene approach with functional materials.

32 nm imprint masks using variable shape beam pattern generators

Imprint lithography has been included on the ITRS Lithography Roadmap at the 32, 22 and 16 nm nodes. Step and Flash Imprint Lithography (S-FIL ®) is a unique method that has been designed from the beginning to enable precise overlay for creating multilevel devices. A photocurable low viscosity monomer is dispensed dropwise to meet the pattern density requirements of the device, thus enabling imprint patterning with a uniform residual layer across a field and across entire wafers. Further, S-FIL provides sub-100 nm feature resolution without the significant expense of multi-element, high quality projection optics or advanced illumination sources. However, since the technology is 1X, it is critical to address the infrastructure associated with the fabrication of templates. For sub-32 nm device manufacturing, one of the major technical challenges remains the fabrication of full-field 1x templates with commercially viable write times. Recent progress in the writing of sub-40 nm patterns using commercial variable shape e-beam tools and non-chemically amplified resists has demonstrated a very promising route to realizing these objectives, and in doing so, has considerably strengthened imprint lithography as a competitive manufacturing technology for the sub 32nm node. Here we report the first imprinting results from sub-40 nm full-field patterns, using Samsungs current flash memory production device design. The fabrication of the template is discussed and the resulting critical dimension control and uniformity are discussed, along with image placement results. The imprinting results are described in terms of CD uniformity, etch results, and overlay.

Toward 22 nm for unit process development using step and flash imprint lithography

Imprint lithography has been included on the ITRS Lithography Roadmap at the 32 and 22 nm nodes. Step and Flash Imprint Lithography (S-FILTM) is a unique method that has been designed from the beginning to enable precise overlay for creating multilevel devices. A photocurable low viscosity monomer is dispensed dropwise to meet the pattern density requirements of the device, thus enabling imprint patterning with a uniform residual layer across a field and across entire wafers. Further, S-FIL provides sub-100 nm feature resolution without the significant expense of multi-element, high quality projection optics or advanced illumination sources. However, since the technology is 1X, it is critical to address the infrastructure associated with the fabrication of templates. This paper addresses steps required to achieve resolution at or below 32 nm. Gaussian beam writers are now installed in mask shops and are being used to fabricate S-FIL templates. Although the throughput of these systems is low, they can nevertheless be applied towards applications such as unit process development and device prototyping. Resolution improvements were achieved by optimizing the ZEP520A resolution and exposure latitude. Key to the fabrication process was the introduction of thinner resist films and data biasing of the critical features. By employing a resist thickness of 70 nm and by negatively biasing features as much as 18 nm, 28 nm half-pitch imprints were obtained. Further processing improvements, including a high resolution lift-off method, show promise for achieving 20 nm half pitch features on a template.

Inspection of 32nm imprinted patterns with an advanced e-beam inspection system

We used electron beam (e-beam) inspection (EBI) systems to inspect nano imprint lithography (NIL) resist wafers with programmed defects. EBI with 10nm pixel sizes has been demonstrated and capability of capturing program defects sized as small as 4nm has been proven. Repeating defects have been captured by the EBI in multiple die inspections to identify the possible mask defects. This study demonstrated the feasibility of EBI as the NIL defect inspection solution of 32nm and beyond.

High Resolution Defect Inspection of Step and Flash Imprint Lithography for 32 nm Half-Pitch Patterning

Imprint lithography has been shown to be an effective method for the replication of nanometer-scale structures from an imprint mask (template) or mold. Step and Flash Imprint Lithography (S-FIL®) is unique in its ability to address both resolution and alignment. Recently overlay across a 200 mm wafer of less than 20nm, 3σ has been demonstrated. Current S-FIL resolution and alignment performance motivates the consideration of nano-imprint lithography as a Next Generation Lithography (NGL) solution for IC production. During the S-FIL process, a transferable image, an imprint, is produced by mechanically molding a liquid UV-curable resist on a wafer. Acceptance of imprint lithography for CMOS manufacturing will require demonstration that it can attain defect levels commensurate with the requirements of cost-effective device production. This report summarizes the result of defect inspections of wafers patterned using S-FIL. Wafer inspections were performed with KLA Tencor- 2132 (KT-2132) and KLA Tencor eS23 (KT-eS32) automated patterned wafer inspection tools. Imprint specific defectivity was shown to be ≤3 cm-2 with some wafers having defectivity of less than 1 cm-2 and many fields having 0 imprint specific defects, as measured with the KT-2132. KT eS32 inspection of 32 nm half pitch features indicated that the random defectivity resulting from the imprint process was low.

The development of full field high resolution imprint templates

Critical to the success of imprint lithography and Step and Flash Imprint Lithography (S-FIL®) in particular is the manufacturing 1X templates. Several commercial mask shops now accept orders for 1X templates. Recently, there have been several publications addressing the fabrication of templates with 32nm and sub 32nm half pitch dimensions using high resolution Gaussian beam pattern generators. Currently, these systems are very useful for unit process development and device prototyping. In this paper, we address the progress made towards full field templates suitable for the fabrication of CMOS circuits. The starting photoplate consisted of a Cr hard mask (≤ 15nm) followed by a thin imaging layer of ZEP 520A. The EBM-5000 and the EBM-6000 variable shape beam pattern generators from NuFlare Technology were used to pattern the images on the substrates. Several key specifications of the EBM-6000, resulting in improved performance over the EBM-5000 include higher current density (70 A/cm2), astigmatism correction in the subfields, optimized variable stage speed control, and improved data handling to increase the maximum shot count limitation. To fabricate the template, the patterned resist serves as an etch mask for the thin Cr film. The Cr, in turn, is used as an etch block for the fused silica. A mesa is formed by etching the non-active areas using a wet buffered oxide etch (BOE) solution. The final step in the template process is a dice and polish step used to separate the plate into four distinct templates. Key steps in the fabrication process include the imaging and pattern processes. ZEP520A was chosen as the e-beam resist for its ability to resolve high resolution images. This paper documents the resolution and image placement capability with the processes described above. Although ZEP520A is slow relative to chemically amplified e-beam resists, it is only necessary to pattern 1/16th the area relative to a 4X reduction mask. Write time calculations for 1X templates have also been performed, and are compared to 4X photomasks.

Defect inspection for imprint lithography using a die to database electron beam verification system

Imprint lithography has been included on the ITRS Lithography Roadmap at the 32 and 22 nm nodes. Step and Flash Imprint Lithography (S-FILTM) is a unique method for printing sub-100nm geometries. Relative to other imprinting processes S-FIL has the advantage that the template is transparent, thereby facilitating conventional overlay techniques. Further, S-FIL provides sub-100nm feature resolution without the significant expense of multielement, high quality projection optics or advanced illumination sources. However, since the technology is 1X, it is critical to address the infrastructure associated with the fabrication of templates. With respect to inspection, although defects as small as 70nm have been detected using optical techniques, it is clear that it will be necessary to take advantage of the resolution capabilities of electron beam inspection techniques. This paper reports the first systematic study of die-to-database electron beam inspection of patterns that were imprinted using an Imprio 250 system. The die-to-database inspection of the wafers was performed on an NGR2100 inspection system. Ultimately, the most desirable solution is to directly inspect the fused silica template. This paper also reports the results on the first initial experiments of direct inspection fused silica substrates at data rates of 200 MHz. Three different experiments were performed. In the first study, large (350-400nm) Metal 1 and contact features were imprinted and inspected as described above. Using a 12 nm pixel address grid, 24 nm defects were readily detected. The second experiment examined imprinted Metal 1 and Logic patterns with dimensions as small as 70nm. Using a pixel address of 3nm, and a defect threshold of 20 nm, a systematic study of the patterned arrays identified problem areas in the design of the pattern layout. Finally, initial inspection of 200mm fused silica patterned substrates has established proof of concept for direct inspection of imprint templates.

Automated imprint mask cleaning for step-and-flash imprint lithography

Step-and-Flash Imprint Lithography (S-FIL) is a promising lithography strategy for semiconductor manufacturing at device nodes below 32nm. The S-FIL 1:1 pattern transfer technology utilizes a field-by-field ink jet dispense of a low viscosity liquid resist to fill the relief pattern of the device layer etched into the glass mask. Compared to other sub 40nm CD lithography methods, the resulting high resolution, high throughput through clustering, 3D patterning capability, low process complexity, and low cost of ownership (CoO) of S-FIL makes it a widely accepted technology for patterned media as well as a promising mainstream option for future CMOS applications. Preservation of mask cleanliness is essential to avoid risk of repeated printing of defects. The development of mask cleaning processes capable of removing particles adhered to the mask surface without damaging the mask is critical to meet high volume manufacturing requirements. In this paper we have presented various methods of residual (cross-linked) resist removal and final imprint mask cleaning demonstrated on the HamaTech MaskTrack automated mask cleaning system. Conventional and non-conventional (acid free) methods of particle removal have been compared and the effect of mask cleaning on pattern damage and CD integrity is also studied.