Ian O 'Connor

IDEA1: A validated SystemC-based system-level design and simulation environment for wireless sensor networks

This article presents IDEA1, a SystemC-based system-level design and simulation framework for WSNs. It allows the performance evaluation (e.g., packet delivery rate, transmission latency and energy consumption) at high level, but with elaborate models of the hardware and software of sensor nodes. Many hardware components are modeled and the IEEE 802.15.4 standard is implemented. IDEA1 uses a clock-based synchronization mechanism to support simulations with cycle accurate communication and approximate time computation. The simulation results have been validated by a testbed of 9 nodes. The average deviation between the IDEA1 simulations and experimental measurements is 4.6%. The performances of IDEA1 have also been compared with NS-2. To provide a similar result (deviation less than 5%) at the same abstraction level, the simulation of IDEA1 is 2 times faster than NS-2. Moreover, with the hardware and software co-simulation feature, IDEA1 provides more detailed modeling of sensor nodes. Finally, IDEA1 is used to study a real-time industrial application in which a wireless sensor and actuator network is deployed on a vehicle to measure and control vibrations. By the simulation, some preliminary designs based on IEEE 802.15.4 protocols and two different hardware platforms are evaluated.

Matrix Nanodevice-Based Logic Architectures and Associated Functional Mapping Method

This article describes a novel computing architecture organization based on nanoscale logic cells. We propose the use of a cluster of matrix arrangements of cells. In order to interconnect such fine-grained logic cells within a matrix, conventional techniques are not suitable due to a large interconnect overhead. Therefore, we propose the use of static and incomplete interconnect topologies to create matrices of cells. We also propose a method to map functions onto such architectures. We then explore the main parameters of the structure (size of matrices and interconnect topologies) and their impact on the main performance metrics (packing efficiency, speed, and fault tolerance). A cluster packing method also allows the evaluation of the number of matrices used by complex functions and the fill factor for various matrix sizes. The analyses show that this approach is particularly suited for matrices of 16 cells interconnected by modified omega networks. We can conclude that this architecture could improve the scalability of traditional FPGAs by a factor of 8.5.

Modeling and simulation of networked low-power embedded systems: a taxonomy

Simulation has been widely adopted for the evaluation of novel protocols or other designs for networked low-power embedded systems, especially for wireless sensor networks (WSNs). A large number of simulation tools have been developed for WSNs in the past few years. However, different tools may emphasize on different features. For example, general network simulators mainly focus on the high-level performance evaluation with certain assumptions, while some SystemC-based simulators have been developed recently to realize the hardware and software co-design of sensor node at the system level. Therefore, it is necessary to study the different modeling methodologies and to distinguish the various features of the existing WSN simulators. In this paper, we propose a taxonomy that categorizes the existing simulation tools into four groups, i.e., network simulators with node models, network simulators with node emulators, node system simulator with network models, and node emulators with network models. To demonstrate the rationality and usability of the proposed taxonomy, we use it to conduct a survey of the existing simulation tools. This study is intended to be comprehensive to cover all important simulation tools.

System Level Exploration for the Integration of Optical Networks on Chip in 3D MPSoC Architectures

Design trends for next-generation multi-processor systems on chip (MPSoC) point to the integration of a large number of processing elements onto a single chip, requiring high-performance interconnect structures for high-throughput communication. On-chip optical interconnect and 3D die stacking are currently considered to be the two most promising paradigms in this design context. New architectures based on these paradigms are currently emerging and new system-level approaches are required for their efficient design. We investigate design tradeoffs for 3D MPSoC integrating optical networks-on-chip (ONoC) and highlight current and short-term design trends. We also propose a system-level design space exploration flow that takes routing capabilities of optical interconnect into account. The resulting application-to-architecture mappings demonstrate the benefits of the presented 3D MPSoC architectures and the efficiency of our system-level exploration flow.

Fine-Grain Reconfigurable Logic Cells Based on Double-Gate MOSFETs

This work presents a new style of gate-level reconfigurable cells based on the double-gate (DG) MOSFET device. The proposed dynamic- and static-logic cells demonstrate significant gate area reductions compared to conventional CMOS lookup table (LUT) techniques (between 80-95%) while configuration memory requirements are also reduced (up to 60%). Simulation results show that it can be used either in low power reconfigurable applications (up to 90% power reduction is possible) or for speeds comparable to those of CMOS-LUTs.

A Protocol Stack Architecture for Optical Network-on-Chip

Optical networks-on-chip (ONoCs) represent an emerging technology for use as a communication platform for systems-on-chip (SoC). It is a novel on-chip communication system where information is transmitted in the form of light, as opposed to conventional electrical networks-on-chip (ENoC). As the ONoC becomes a candidate solution for the communication infrastructure of the SoC, the development of proper hierarchical models and tools for its design and analysis, specific to its heterogeneous nature, becomes a necessity. This chapter studies a class of ONoCs that employ a single central passive-type optical router using wavelength division multiplexing (WDM) as a routing mechanism. A novel protocol stack architecture for the ONoC is presented. The proposed protocol stack is a 4-layered hardware stack consisting of the physical layer, the physical-adapter layer, the data link layer, and the network layer. It allows the modular design of each ONoC building block, thus boosting the interoperability and design reuse of the ONoC. Adapting this protocol stack architecture, this chapter introduces the micro-architecture of a new router called electrical distributed router (EDR) as a wrapper for the ONoC. Then, the performance of the ONoC layered architecture has been evaluated both at system-level (network latency and throughput) and at the physical (optical) level. Experimental results prove the scalability of the ONoC and demonstrate that the ONoC is able to deliver a comparable bandwidth or even better (in large network sizes) to the ENoC. The proposed protocol stack has been modeled and integrated inside an industrial simulation environment (ST OCCS GenKit) using an industrial standard (VSTNoC) protocol.