Igor Aleksejev

FPGA-based synthetic instrumentation for board test

This paper studies a new approach for board-level test based on synthesizable embedded instruments implemented on FPGA. This very recent methodology utilizes programmable logic devices (FPGA) that are usually available on modern PCBs to a large extent. The purpose of an embedded instrument is to carry out a vast portion of test application related procedures, perform measurement and configuration of system components thus minimizing the usage of external test equipment. By replacing traditional test and measurement equipment with embedded synthetic instruments it is possible not only to achieve the significant reduction of test costs but also facilitate high-speed and at-speed testing. We detail the motivation and classify the FPGA-based instrumentation into different categories based on the implementation and application domains. Experimental results show the efficiency of this approach.

Fast extended test access via JTAG and FPGAs

This paper describes a new test access protocol for system-level testing of printed circuit boards for manufacturing defects. We show that the protocol can be based on standard Boundary Scan (BS) instructions and test access mechanism (TAM). It means that the methodology does not require any changes/redesign of hardware and can be immediately implemented in the electronic manufacturing. Our solution needs however a proper software support and availability of programmable devices (FPGAs, CPLDs, etc.) on the board under test. The new technique dramatically extends the applicability of BS testing in the reality of modern complex on-board data transfer buses and protocols. Potentially, it can also increase the speed of in-system programming of flash memories and other tasks that are traditionally performed using BS.

Virtual reconfigurable scan-chains on FPGAs for optimized board test

This paper presents a method for optimization of board-level scan-test with the help of reconfigurable scan-chains (RSCs) implemented in a programmable logic of FPGA. Despite that the RSC concept is a well-known solution for scan-based test time reduction, the usage of RSC may lead to un-acceptable hardware overhead. In our work, we are targeting a completely new approach of exploiting on-board FPGA resources that being unconfigured are typically available during the manufacturing test phase for carrying out tests using temporarily implemented virtual RSC structures. As the allocated FPGA logic is re-claimed for functional use after the test is finished, the presented method delivers all the advantages of RSCs at no extra HW cost. Experimental results show that the proposed virtual RSCs can fit into all available commercial FPGAs providing a significant overall test time reduction in comparison with traditional Boundary Scan approach.

Turning JTAG inside out for fast extended test access

This paper describes a new test access protocol for system-level testing of printed circuit boards for manufacturing defects. We show that the protocol can be based on standard Boundary Scan (BS) instructions and test access mechanism (TAM). It means that the methodology does not require any changes/redesign of hardware and can be immediately implemented in the electronic manufacturing. Our solution needs however a proper software support and availability of programmable devices (FPGAs, CPLDs, etc.) on the board under test. The new technique dramatically extends the applicability of BS testing in the reality of modern complex on-board data transfer buses and protocols. Potentially, it can also increase the speed of in-system programming of flash memories and other tasks that are traditionally performed using BS.

Run-time reconfigurable instruments for advanced board-level testing

In recent years embedded instrumentation becomes a cutting-edge technology in the field of testing and measurements. In this paper, we propose a classification of different implementations of FPGA-based embedded instruments based on the format they are delivered to an end-user. Up to now, instruments provided as soft core IPs and hard macro blocks only were proposed. In this work, we present novel run-time reconfigurable (RTR) instruments, which are distributed as pre-compiled readyto-use bitstreams, and study their applicability for boardlevel test tasks. These instruments are designed in a special way that allows on-the-fly adaptation of the instrument to test the particular product. With the help of these RTR instruments one can considerably improve quality of tests for printed circuit board assemblies as well as reduce test time. Being integrated to the test setup, the instruments represent an automated and low-cost complementary solution for testing of complex high-performance boards and systems.

Embedded synthetic instruments for Board-Level testing

The main purpose of this paper is to refine the benefits of the FPGA-based synthetic instrumentation concept (see Section 1) proposed by us earlier [1] as well as to provide some new experimental data based on real industrial designs to show the efficiency of our methodology (see Section 2).

Reseeding using compaction of pre-generated LFSR sub-sequences

Built-In Self-Test (BIST) techniques are often based on pseudo-random pattern generators, which represent simple structures that can generate necessary test stimuli for a device under test (DUT). For some designs, however, additional measures of fault coverage improvement have to be applied. LFSR reseeding is a popular technique due to its ability to considerably improve both the fault coverage and test application time by embedding specific vectors into the pseudorandom sequence. Proper selection of LFSR seeds is the key aspect in a successful reseeding scheme. In this paper, we present our approach to reseeding optimization that is based on compaction of pre-generated LFSR sub-sequences in order to select a minimal subset of to be included into the final solution. The proposed approach relies on the branch-and-bound search technique, which can provide the optimal compaction for a given test setup. Alternatively, it can run for a limited time in a heuristic mode, producing intermediate results. Experiments show that applied heuristics can yield optimal or quasi-optimal solutions in polynomial time. These solutions outperform previously published results for a similar reseeding approach.

On coverage of timing related faults at board level

In this paper, we demonstrate a clear gap in board level test coverage under category of timing related faults (TRFs). Although there are techniques that are capable to detect TRFs, there is no fault coverage metrics to quantify the quality of these techniques. To do that, we propose an easy-to-implement interconnect-level fault model extension towards TRFs. This extension can be integrated into existing test coverage models providing additional information on coverage of timing-related faults.

Application of Sequential Test Set Compaction to LFSR Reseeding

LFSR reseeding techniques are often applied in BIST due to their ability to considerably improve the fault coverage and test application time by embedding specific vectors into the pseudorandom sequence. The efficiency of a typical reseeding scheme to a large extent depends on the seed selection and consequent test sequence optimization algorithms. This paper proposes a novel efficient reseeding optimization algorithm that is based on test compaction techniques for sequential designs. The proposed approach relies on the branch-and-bound search technique, which can provide the optimal test set compaction solution for a given test setup. Alternatively, it can run for a limited time in a heuristic mode, producing intermediate results. Experiments show that applied heuristics can yield optimal or quasi-optimal solutions in polynomial time. These solutions outperform previously published reseeding and hybrid BIST results.

Optimization of Boundary Scan Tests Using FPGA-Based Efficient Scan Architectures

This paper presents a method for optimization of board-level scan test with the help of reconfigurable scan-chains (RSCs) implemented in a programmable logic of FPGA. Despite that the RSC concept is a well-known solution for scan-based test time reduction, the usage of RSC may lead to un-acceptable hardware overhead. In our work, we are targeting a completely new approach of exploiting on-board FPGA resources that being unconfigured are typically available during the manufacturing test phase for carrying out tests using temporarily implemented virtual RSC structures. As the allocated FPGA logic is re-claimed for functional use after the test is finished, the presented method delivers all the advantages of RSCs at no extra hardware cost. Experimental results show that the proposed virtual RSCs can fit into all available commercial FPGAs providing a significant test time reduction in comparison with state-of-the-art Boundary Scan test tecnique.