Ikuko Inoue

Low-leakage-current and low-operating-voltage buried photodiode for a CMOS imager

A low-leakage current and low-operating-voltage buried-photodiode structure of CMOS image sensors has been developed. The new structure adopted a modified fabrication process as well as an additional shallow p+ layer structure that covers the entire surface of the deep n-type photodiode. The required operating voltage for complete charge transfer from the photodiode is 3.3 V. Furthermore, the leakage current level allows high-quality images comparable to those of CCD image sensors.

A 60 mW 10 b CMOS image sensor with column-to-column FPN reduction

A 60 mW 10b 660(H)/spl times/490(v) pixel digital CMOS image sensor with column-to-column FPN reduction introduces the double inverting amplifier with double clamp circuit for reduction of column-to-column fixed pattern noise (dark FPN and light FPN). It operates with a 3.3 V power supply and has 60 mW power consumption. This sensor is uses 0.6 /spl mu/m, triple-poly-silicon, double-metal CMOS technology.

New effects of trench isolated transistor using side-wall gates

In order to realize a high performance switching transistor, a new trench isolated transistor with side-wall gates has been developed. In this transistor with a triple-gate structure, the side-wall of the trench is used as an extra-channel region. The new effects of trench isolated transistor with a triple-gate structure have been described. The advantages of this transistor are excellent cutoff characteristics, a small substrate bias effect and high reliability characteristics. It is found that the side-wall gate along the channel edge plays an important role for increasing the gate controllability and for decreasing the concentration of the electric field at the drain.

Effects of a new trench-isolated transistor using sidewall gates

In this structure, the sidewall of the trench is used as an extra channel region. The sidewall gate electrode, which covers the sharp convex corner of the trench, increases the electric field at the channel edge. The advantages of this transistor are excellent cutoff characteristics, a small substrate bias effect, and high reliability (compared with the LOCOS-isolated transistor). The sidewall gate along the channel edge plays an important role in increasing gate controllability and decreasing the electric field at the drain. >

A 2/3-inch 2M-pixel STACK-CCD imager

Shrinking pixel size in conventional CCD imagers degrades device performance. Unsatisfactory smear noise of -90 dB is attained in a 2/3-inch 2M pixel CCD imager. The STACK-CCD imager has a great advantage regarding this problem. A 100% aperture ratio and low smear noise are maintained regardless of future pixel shrinking, because CCD scanning circuits are overlaid with an amorphous silicon (a-Si) photoconversion layer.<<ETX>>

A 3.7/spl times/3.7 /spl mu/m/sup 2/ square pixel CMOS image sensor for digital still camera application

Systems such as digital still cameras, robots, etc. require low-cost, low-power and high-resolution. This CMOS image sensor has reduced cell size. The sensor is fabricated using 0.6 /spl mu/m, triple-poly-silicon, double-metal CMOS process technology. The sensor has 3.7/spl times/3.7 /spl mu/m/sup 2/ pixels. It operates with one 3.3V power supply and has less than 30mW power dissipation.

A 2/3-in 2 million pixel STACK-CCD HDTV imager

A 2/3-in optical format 2 M pixel STACK-CCD imager has been developed. The STACK-CCD imager, overlaid with an amorphous silicon photoconversion layer, realizes a large signal charge handling capability of 1.0/spl times/10/sup 5/ electrons, a -140 dB smear noise and a 90 dB dynamic range with a newly introduced device configuration and its unique operation. The 5.0 /spl mu/m(H)/spl times/5.2 /spl mu/m(V) unit pixel imager with sufficiently low image lag has been realized by a novel bias charge injection scheme These device performances are the best ever achieved by a CCD HDTV imager. This is the first such imager satisfying the device performances required for a practical use 2/3-in 2 M pixel HDTV imager. >

A 2 M-pixel two-level vertically integrated HDTV image sensor

A 2 Mpixel two-level CCD (charge-coupled device) image sensor which has no capacitive image lag is discussed. Image lag is reduced to 0.4% and the dynamic range expanded from 72 dB to 110 dB. A schematic diagram of this device is shown. The pixel structure adopts an additional storage-diode-resetting gate (SRG) and bias-charge-injecting diode (CID) formed adjacent to a vertical CCD. A single CID is shared by two horizontally adjacent pixels, allowing the charge to be injected into two storage diodes simultaneously.<<ETX>>

Low Gr/Gb sensitivity imbalance 3.2M CMOS image sensor with 2.2μm pixel

For CMOS image sensors with pixel size under 3μm pixel, the pixel architecture in which several photodiodes share floating diffusion and transistors tends to be adopted in order to improve full well capacity and sensitivity. In spite even in the aforementioned advantage, adoption of the architecture may result in sensitivity imbalance between the shared photodiodes. On reproduced images obtained by the shared pixel architecture, sensitivity imbalance between Gr and Gb photodiodes in Bayer CFA is often conspicuous, because the imbalance results in horizontal pattern noise. We developed a low Gr/Gb sensitivity imbalance 3.2M CMOS Image Sensor with 2.2μm pixel. The pixel has the structure which is optically designed carefully in order to prevent light diffraction in pixel. According to a simulation result, read transistor gate for pixels with red color filter has an edgeless layout, because longer wave length light incident to the red pixels. For the optical design, electromagnetic analytical simulation was used because wave-optical effect cannot be ignored for the small pixel below 3μm. Gr/Gb sensitivity imbalance was measured for both the developed sensor and conventional sensor in visible light range. It was measured that the Gr/Gb sensitivity imbalance is below measurement limit.