Nobuo Nakamura

A high-sensitivity CMOS image sensor with gain-adaptive column amplifiers

A high-sensitivity CMOS image sensor using gain-adaptive column amplifiers is presented and tested. The use of high gain for the column amplifier reduces input-referred random noise, and when coupled with a column-based digital noise cancellation technique, also reduces fixed pattern noise. An experimental application of the circuit using 0.25-/spl mu/m CMOS technology with pinned photodiodes gave an rms random noise of 263 /spl mu/V and an rms fixed pattern noise of 50 /spl mu/V.

A 1/4 inch 330 K square pixel progressive scan CMOS active pixel image sensor

CMOS active pixel sensors (APS) have attracted special attention in recent years because of monolithic integration of controlling, driving and signal processing circuitry within a single sensor chip. However, a large pixel area is required for implementing row select, charge reset and amplification elements in a pixel. Further pixel size shrinkage is necessary, especially for applications like consumer-use digital still photography. Reduced cell size is reported for the television, but the device operates only in the interlace scan mode. This consumer-use 1/4 inch 640(H)x480(V) pixel active pixel sensor has a 5.6x5.6/spl mu/m/sup 2/ pixel. The imager operates with a 5.0V single power supply and less than 30mW dissipation. The sensor uses 0.6/spl mu/m, double poly-silicon, triple-metal CMOS process technology.

A column-based pixel-gain-adaptive CMOS image sensor for low-light-level imaging

A 0.25 /spl mu/m technology CMOS image sensor employs a 4.2 /spl mu/m pitch pinned-photodiode pixel. A column amplifier and digital domain processing reduce the fixed pattern noise to 55 /spl mu/V. The saturation voltage is 1 V with a 2.5 V supply voltage, and the dynamic range is 69 dB.

A 60 mW 10 b CMOS image sensor with column-to-column FPN reduction

A 60 mW 10b 660(H)/spl times/490(v) pixel digital CMOS image sensor with column-to-column FPN reduction introduces the double inverting amplifier with double clamp circuit for reduction of column-to-column fixed pattern noise (dark FPN and light FPN). It operates with a 3.3 V power supply and has 60 mW power consumption. This sensor is uses 0.6 /spl mu/m, triple-poly-silicon, double-metal CMOS technology.

A 2/3-inch 2M-pixel STACK-CCD imager

Shrinking pixel size in conventional CCD imagers degrades device performance. Unsatisfactory smear noise of -90 dB is attained in a 2/3-inch 2M pixel CCD imager. The STACK-CCD imager has a great advantage regarding this problem. A 100% aperture ratio and low smear noise are maintained regardless of future pixel shrinking, because CCD scanning circuits are overlaid with an amorphous silicon (a-Si) photoconversion layer.<<ETX>>

A 2/3-in 2 million pixel STACK-CCD HDTV imager

A 2/3-in optical format 2 M pixel STACK-CCD imager has been developed. The STACK-CCD imager, overlaid with an amorphous silicon photoconversion layer, realizes a large signal charge handling capability of 1.0/spl times/10/sup 5/ electrons, a -140 dB smear noise and a 90 dB dynamic range with a newly introduced device configuration and its unique operation. The 5.0 /spl mu/m(H)/spl times/5.2 /spl mu/m(V) unit pixel imager with sufficiently low image lag has been realized by a novel bias charge injection scheme These device performances are the best ever achieved by a CCD HDTV imager. This is the first such imager satisfying the device performances required for a practical use 2/3-in 2 M pixel HDTV imager. >

A low driving voltage CCD with single layer electrode structure for area image sensor

A new single layer electrode two-phase CCD was studied for the purpose of realizing low driving voltage operation in inter-line transfer CCD (IT-CCD) image sensor aiming for low power consumption. Conventional H-CCD with overlapping double layer electrode structure have not achieved signal charge transfer at very low driving voltage below 2 V due to appearance of potential pocket under the inter-electrode gap yet. The new CCD employs a new channel doping profile for potential pocket suppression at the inter-electrode gap. The new CCD also employs a stepped-oxide structure having a single layer transfer electrode covering both a thin gate oxide forming storage region and a thinner gate oxide forming barrier region. The inter-electrode gap of single layer electrode was decreased to as small as 0.3 /spl mu/m. As a result of these measures, a fabricated 1/3 in format 270 K pixel IT-CCD image sensor reproduces a fine video image even when it is operated at a driving voltage as low as 1.8 V.

A single-layer metal-electrode CCD image sensor

A small pixel is required to reduce CCD image sensor chip size for commercial application. However, the shrinkage of pixel size adversely affects such characteristics as smear noise, sensitivity and charge-handling capability. Furthermore, a conventional overlapping double-layer polysilicon (polySi) electrode is complicated and difficult to fabricate for CCD image sensors. For process step simplicity of the transfer electrodes, aiming at low cost sensors and the smear noise reduction, a single-layer metal-electrode CCD image sensor is introduced.

Dark current fixed pattern noise reduction for the 2/3-in two-million pixel HDTV STACK-CCD imager

The fixed pattern noise reduction methods, surrounding channel stop structure and the hole accumulation operation, are proposed and evaluated for the 2/3-in two-million pixel STACK-CCD HDTV imager. The surrounding channel stop structure is surrounded by the channel stop region to suppress the fluctuation of the mean dark current from Si-SiO/sub 2/ interface and the depletion layer of p-n junction. The measured fixed pattern note (FPN) and signal-to-noise (S/N) ratio are improved from 45 electrons down to 19 electrons and from 49 dB up to 54 dB under the condition of F.8 and 2000 lux at 333 K, respectively. Therefore, the 2/3-in two-million pixel HDTV handy-type color camera with high S/N ratio and low FPN can be obtained.

Random noise generation mechanism for a CCD imager with an incomplete transfer-type storage diode

A random noise for a CCD imager with an incomplete transfer-type storage diode is theoretically and experimentally discussed. The theoretical result based on the Fermi-Dirac distribution function is in good agreement with the well known experimental result as a kTC noise, which is equal to the square root of kTC/2. It is also shown that the random noise in the storage diode is dependent on the amount of the signal charge, and can be reduced for the small signal charge. Moreover, a small signal reset operation (SSR operation) is newly proposed to suppress the capacitive-image-lag and larger random noise. The reproduced image with the high signal-to-noise (S/N) ratio is obtained for a STACK-CCD imager with the small signal reset operation.