Michio Sasaki

A 60 mW 10 b CMOS image sensor with column-to-column FPN reduction

A 60 mW 10b 660(H)/spl times/490(v) pixel digital CMOS image sensor with column-to-column FPN reduction introduces the double inverting amplifier with double clamp circuit for reduction of column-to-column fixed pattern noise (dark FPN and light FPN). It operates with a 3.3 V power supply and has 60 mW power consumption. This sensor is uses 0.6 /spl mu/m, triple-poly-silicon, double-metal CMOS technology.

A 2/3-inch 2M-pixel STACK-CCD imager

Shrinking pixel size in conventional CCD imagers degrades device performance. Unsatisfactory smear noise of -90 dB is attained in a 2/3-inch 2M pixel CCD imager. The STACK-CCD imager has a great advantage regarding this problem. A 100% aperture ratio and low smear noise are maintained regardless of future pixel shrinking, because CCD scanning circuits are overlaid with an amorphous silicon (a-Si) photoconversion layer.<<ETX>>

A single-layer metal-electrode CCD image sensor

A small pixel is required to reduce CCD image sensor chip size for commercial application. However, the shrinkage of pixel size adversely affects such characteristics as smear noise, sensitivity and charge-handling capability. Furthermore, a conventional overlapping double-layer polysilicon (polySi) electrode is complicated and difficult to fabricate for CCD image sensors. For process step simplicity of the transfer electrodes, aiming at low cost sensors and the smear noise reduction, a single-layer metal-electrode CCD image sensor is introduced.

Analysis of low fixed pattern noise cell structures for photoconversion layer overlaid CCD or CMOS image sensors

A new low fixed pattern noise (FPN) cell structure, which can be used for photoconversion layer overlaid CCD or CMOS image sensors, was proposed and analyzed with a two-dimensional (2-D) device simulator. One of the most serious problems for this type of image sensor is the mixing of signal charges of neighboring cells during signal charge readout. The magnitude of signal mixing was as much as 20% for the conventional 2/3-in 2-million pixel STACK-CCD cell structure. FPN was very visible as a result of this signal mixing. This time, a new cell structure was proposed and analyzed to reduce signal mixing and FPN. It was possible to reduce signal mixing to a low value of 0.7% of the signal level using the new cell structure.

Hg-Sensitized Photochemical Vapor Deposition Application to Hydrogenated Amorphous Silicon Photoconversion Layer Overlaid on Charge Coupled Device

An Hg-sensitized photochemical vapor deposition method has been developed which has enabled a hydrogenated amorphous silicon photoconversion layer to be overlaid on a charge coupled device (CCD) imager, without a pixel separation structure. This chemical vapor deposition (CVD) method has been used to realize imaging devices with high sensitivity and high resolution for high-definition TV.

Solid State Imaging Techniques. Study of Signal-Layer Metal-Electrode CCD Image Sensor.

A single-layer metal-electrode CCD image sensor was studied with the purpose of simplifying the steps in the production process with the aim of achieving low-cost sensors and supplressing smear noise. The inter-electrode gap of the single-layer electrode was decreased to 0.3 micrometer to achieve charge-transfer efficiency of unity. Boron ion-implantation which is self-aligned to the interelectrode gap was introduced to suppress degradation in charge-transfer efficiency. A reduction in the number of process steps needed to fabricate a 1/3-inch-format 360K-pixel interline transfer CCD image sensor was achieved. Vertical resolution was 350 TV lines. Low smear noise of-108dB was obtained.

A 2/3 inch 400 k pixel sticking-free stack-CCD image sensor

A 2/3-in 400-k pixel-stack-CCD (charge coupled device) image sensor that has bias charge injection into the a-Si layer is described. Because the bias charges fill the deep level traps in advance, image sticking is reduced to imperceptible levels 0.3 s after 10000*standard incident light is turned off. This device has the frame interline transfer architecture; the V-CCD (vertical-CCD) registers are used not only as signal charge transfer paths in the vertical-blanking period, but also as blooming drains in the signal-charge-integration period. The equivalent circuit of the stack-CCD sensor is shown along with a cross-section view of the unit pixel in the stack-CCD sensor. >