Hisanori Ihara

Low-leakage-current and low-operating-voltage buried photodiode for a CMOS imager

A low-leakage current and low-operating-voltage buried-photodiode structure of CMOS image sensors has been developed. The new structure adopted a modified fabrication process as well as an additional shallow p+ layer structure that covers the entire surface of the deep n-type photodiode. The required operating voltage for complete charge transfer from the photodiode is 3.3 V. Furthermore, the leakage current level allows high-quality images comparable to those of CCD image sensors.

A 2/3-inch 2M-pixel STACK-CCD imager

Shrinking pixel size in conventional CCD imagers degrades device performance. Unsatisfactory smear noise of -90 dB is attained in a 2/3-inch 2M pixel CCD imager. The STACK-CCD imager has a great advantage regarding this problem. A 100% aperture ratio and low smear noise are maintained regardless of future pixel shrinking, because CCD scanning circuits are overlaid with an amorphous silicon (a-Si) photoconversion layer.<<ETX>>

A 3.7/spl times/3.7 /spl mu/m/sup 2/ square pixel CMOS image sensor for digital still camera application

Systems such as digital still cameras, robots, etc. require low-cost, low-power and high-resolution. This CMOS image sensor has reduced cell size. The sensor is fabricated using 0.6 /spl mu/m, triple-poly-silicon, double-metal CMOS process technology. The sensor has 3.7/spl times/3.7 /spl mu/m/sup 2/ pixels. It operates with one 3.3V power supply and has less than 30mW power dissipation.

A 2/3-in 2 million pixel STACK-CCD HDTV imager

A 2/3-in optical format 2 M pixel STACK-CCD imager has been developed. The STACK-CCD imager, overlaid with an amorphous silicon photoconversion layer, realizes a large signal charge handling capability of 1.0/spl times/10/sup 5/ electrons, a -140 dB smear noise and a 90 dB dynamic range with a newly introduced device configuration and its unique operation. The 5.0 /spl mu/m(H)/spl times/5.2 /spl mu/m(V) unit pixel imager with sufficiently low image lag has been realized by a novel bias charge injection scheme These device performances are the best ever achieved by a CCD HDTV imager. This is the first such imager satisfying the device performances required for a practical use 2/3-in 2 M pixel HDTV imager. >

Color cross-talk simulation analysis for image sensor

The color cross-talk simulation analysis was carried out. The color cross-talk was depended on the p-well potential profile. The color cross-talk has a minimum value around 2.3 micrometers junction depth of p-well. The color cross-talk can be improved by the suitable well structure.

Electric field concentration at electrode edge with decreasing amorphous silicon defect density

Abstract Many studies have concentrated on the decrease in a-Si defect density. However, several a-Si image sensors, such as the 2M-pixel charge coupled device (CCD) image sensor, suffer from the following problem: a decrease in defect density causes an increase in reverse biased current. Therefore, a trial was carried out to calculate the electric field around the edge of the bottom electrode and, so far, have obtained the following results: (1) a decrease in defect density caused an increase in the electric field concentration at the edge of the electrode, and (2) the electric field concentration was improved by optimizing shape of the electrode edge. In addition, it was confirmed that relaxation of the electric field concentration was observed in the prepared sample.

The observation of plasma induced defect density at a-Si:H interface by quasi-static C-V measurement

Abstract ASi i-p diode with i/i interface in i-a-Si layer is prepared. The upper i-a-Si layer is deposited by the plasma enhanced chemical vapor deposition method. This sample is evaluated by quasi-static capacitance versus voltage measurement. It has been found that the plasma induced defect density in the sample can be observed by this method. A 4 to 5 × 10 9 cm −2 increase in defect density at i/i interface is observed. In addition, it has been found that the quantity of plasma damage is substrate dependent.

A 2/3 inch 400 k pixel sticking-free stack-CCD image sensor

A 2/3-in 400-k pixel-stack-CCD (charge coupled device) image sensor that has bias charge injection into the a-Si layer is described. Because the bias charges fill the deep level traps in advance, image sticking is reduced to imperceptible levels 0.3 s after 10000*standard incident light is turned off. This device has the frame interline transfer architecture; the V-CCD (vertical-CCD) registers are used not only as signal charge transfer paths in the vertical-blanking period, but also as blooming drains in the signal-charge-integration period. The equivalent circuit of the stack-CCD sensor is shown along with a cross-section view of the unit pixel in the stack-CCD sensor. >