Inna V. Babich

Self-aligned n-channel germanium MOSFETs with a thin Ge oxynitride gate dielectric and tungsten gate

In this letter, we report self-aligned n-channel germanium (Ge) MOSFETs with a thin Ge oxynitride gate dielectric and tungsten gate electrode. Excellent off-state current is achieved through the reduction of junction leakage. For the first time, we have demonstrated an n-channel Ge MOSFET with a subthreshold slope of 150 mV/dec and an on-off current ratio of /spl sim/10/sup 4/.

High-capacity, self-assembled metal-oxide-semiconductor decoupling capacitors

We combine nanometer-scale polymer self assembly with advanced semiconductor microfabrication to produce metal-oxide-semiconductor (MOS) capacitors with accumulation capacitance more than 400% higher than planar devices of the same lateral area. The self assembly technique achieves this degree of enhancement using only standard processing techniques, thereby obviating additional process complexity. These devices are suitable for use as on-chip power supply decoupling capacitors, particularly in high-performance silicon-on-insulator technology.

Low voltage, scalable nanocrystal flash memory fabricated by templated self assembly

We introduce a new method for building nanocrystal flash memory devices that achieves precise control of nanocrystal size and position. Nanocrystal dimensions are defined via polymer self assembly, facilitating device scaling. Devices exhibit low voltage memory operation with promising retention and endurance properties.

Two gates are better than one [double-gate MOSFET process]

A planar self-aligned double-gate MOSFET process has been implemented where a unique sidewall source/drain structure (S/D) permits self-aligned patterning of the back-gate layer after the S/D structure is in place. This allows coupling the silicon thickness control inherent in a planar, unpatterned layer with VLSI self-alignment techniques and also gives independently controlled front and back gates. The demanding structure led to process innovations primarily in front-end CMP, where planarity within 5 nm was achieved on an 8-in diameter wafer as well as in silicided silicon source/drain sidewalls, with minimal encroachment of the silicide. Double-gate FET (DGFET) operation is demonstrated, with good transport at both interfaces. Dense circuit layouts are achieved with multifinger devices, and logic inverters with back-gate-controlled load current as well as NOR logic using the two gates of a single transistor as inputs are demonstrated.

Integrated, variable-reluctance magnetic minimotor

The use of lithography and electroplating to fabricate variable-reluctance, nearly planar, integrated minimotors with 6-mm-diameter rotors on silicon wafers is described. The motors consist of six electroplated Permalloy® horseshoe-shaped cores that surround the rotor. Copper coils are formed around each core. The Permalloy and copper electroplating baths, electroplating seed layers, and through-mask plating techniques are similar to those used to fabricate inductive thin-film heads. High-aspect-ratio optical lithography or X-ray lithography was used to form the various resist layers. The rotors were fabricated separately, released from the substrate, and then slipped onto the shaft, which was plated as part of the stator fabrication process. The fabrication processes for stator and rotor are described in this paper, and initial minimotor operation data are presented.

Aggressively scaled (0.143 /spl mu/m/sup 2/) 6T-SRAM cell for the 32 nm node and beyond

A 0.143 /spl mu/m/sup 2/ 6T-SRAM cell has been fabricated using a planar SOI technology with mixed electron-beam and optical lithography. This is the smallest functional 6T-SRAM cell ever reported - consistent with cell areas beyond the 32 nm technology node. Enabling process features include a 25 nm SOI layer, shallow trench isolation (STI), 45 nm physical gates with ultra-narrow 15 nm spacers, novel extremely thin cobalt disilicide, 50 nm tungsten plug contacts, and damascene copper interconnects. Device threshold voltages (V/sub T/) and cell beta ratio (/spl beta/) are optimized for cell stability at these aggressive ground rules. The 0.143 /spl mu/m/sup 2/ 6T-SRAM cell exhibits a static noise margin (SNM) of 148 mV at V/sup DD/=1.0 V.

Looking into the crystal ball: future device learning using hybrid e-beam and optical lithography (Keynote Paper)

Semiconductor process development teams are faced with increasing process and integration complexity while the time between lithographic capability and volume production has remained more or less constant over the last decade. Lithography tools have often gated the volume checkpoint of a new device node on the ITRS roadmap. The processes have to be redeveloped after the tooling capability for the new groundrule is obtained since straight scaling is no longer sufficient. In certain cases the time window that the process development teams have is actually decreasing. In the extreme, some forecasts are showing that by the time the 45nm technology node is scheduled for volume production, the tooling vendors will just begin shipping the tools required for this technology node. To address this time pressure, IBM has implemented a hybrid-lithography strategy that marries the advantages of optical lithography (high throughput) with electron beam direct write lithography (high resolution and alignment capability). This hybrid-lithography scheme allows for the timely development of semiconductor processes for the 32nm node, and beyond. In this paper we will describe how hybrid lithography has enabled early process integration and device learning and how IBM applied e-beam & optical hybrid lithography to create the worlds smallest working SRAM cell.

Polymer self assembly in semiconductor microelectronics

Integration of polymer self assembly with semiconductor processing enables sub-lithographic patterning of integrated circuit (IC) device elements and offers a non-traditional pathway to performance improvements (Black, 2005). We discuss target applications including surface-roughening for on-chip decoupling capacitors (Black et al., 2004), patterning nanocrystal floating gates for FLASH devices (Guarini et al., 2003), and defining FET channel arrays (Black, 2005)

Fabrication challenges for next-generation devices: Microelectromechanical systems for radio-frequency wireless communications

With wireless communications becoming an important technology and growth engine for the semiconductor industry, many semiconductor companies are developing technologies to differentiate themselves in this area. One means of accomplishing this goal is to find a way to integrate passive components, which currently make up more than 70% of the discrete components in a wireless handset, directly on-chip thereby greatly simplifying handsets. While a number of technologies are being investigated to allow on-chip integration, microelectromechanical systems technologies are an important part of this development effort. They have been used to create switches, filters, local oscillators, variable capacitors, and high-quality inductors, to name a few examples. The lithography requirements for these devices are very different than those found in standard semiconductor fabrication with the most important involving patterning over extreme topography. We discuss some of the fabrication challenges for these devices as well as some approaches that have been demonstrated to satisfy them.

New family of non-chemically amplified resists

Non-chemically amplified resists offer advantages over chemically-amplified (CA) resists because they are less susceptible to temperature variations and contaminants. In order for non-CA resists to be viable, they have to perform lithographically at an equivalent level with the CA resists from the point of view of quantum yield, resolution and etch resistance. We report here on new non-CA resists based on polymer esters that undergo deesterification to the corresponding acids upon exposure to UV, x-ray and e-beam radiation. The efficiency of the radiation reaction is surprisingly high. The resulting poly acids are base soluble and can be employed as positive working resists. The resists are composed of polymers and copolymers of methacrylate esters. The sensitivity of one derivative to x-ray is 75 mJ/cm2 and to e-beam is 1.0 (mu) C/cm2 at 10 KV. Best resolution obtained was 125 nm with x-ray radiation.