E. Sikorski

Self-aligned n-channel germanium MOSFETs with a thin Ge oxynitride gate dielectric and tungsten gate

In this letter, we report self-aligned n-channel germanium (Ge) MOSFETs with a thin Ge oxynitride gate dielectric and tungsten gate electrode. Excellent off-state current is achieved through the reduction of junction leakage. For the first time, we have demonstrated an n-channel Ge MOSFET with a subthreshold slope of 150 mV/dec and an on-off current ratio of /spl sim/10/sup 4/.

Low voltage, scalable nanocrystal flash memory fabricated by templated self assembly

We introduce a new method for building nanocrystal flash memory devices that achieves precise control of nanocrystal size and position. Nanocrystal dimensions are defined via polymer self assembly, facilitating device scaling. Devices exhibit low voltage memory operation with promising retention and endurance properties.

FinFET performance advantage at 22nm: An AC perspective

At the 22 nm node, we estimate that superior electrostatics and reduced junction capacitance in FinFETs may provide a 13~23% reduction in delay relative to planar FETs. However, this benefit is offset by enhanced gate-to-source/drain capacitance (Cgs) in FinFETs. Here, we measure FinFET Cgs capacitance at 22 nm-like dimensions and determine that, with optimization, the FinFET capacitance penalty can be limited to <6%, resulting in an overall advantage of up to 17% over a planar technology.

High performance FDSOI CMOS technology with metal gate and high-k

A high performance FDSOI CMOS technology featuring metal gate electrodes and high-k gate dielectrics is presented. Work-function tuning is accomplished by materials and process modification to achieve appropriate threshold voltages for FDSOI CMOS. The gate stacks exhibit an extremely thin effective inversion thickness (T/sub inv/) down to 14A with a gate leakage current of 0.2A/cm/sup 2/. This represents a six order of magnitude leakage reduction compared to Poly/SiO/sub 2/. By optimizing the gate stack, the highest unstrained electron mobility is realized (207cm/sup 2/A/s at E/sub eff/=1Mv/cm) at T/sub inv/=14A. Drive currents of 1050/spl mu/A//spl mu/m and 770/spl mu/A//spl mu/m at I/sub off/ of 90nA//spl mu/m and 28nA//spl mu/m are achieved for nMOS and pMOS respectively. This is the highest reported pFET drive current for metal gate transistors with high-k gate dielectrics. We also present FDSOI metal gate high-k ring oscillators and SRAM cells with static noise margin (SNM) of 328mV at V/sub dd/=1,2V.

Poly-Si/AlN/HfSiO Stack for Ideal Threshold Voltage and Mobility in Sub-100 nm MOSFETs

A scalable poly-Si/AlN/HfSiO gate stack, implementing a new aluminum nitride (AlN) cap layer, combined with oxygen diffusion barrier, halo and counter doping engineering, high temperature spike anneal for gate and junction activation, and optional inverted gate implant, has been successfully developed to fully offset the large threshold voltage (Vt) shifts in poly-Si/HfSiO devices and achieve good thickness scalability and gate stack stability. The new AlN cap layers provide better PFET Vt control than, for example, Al2O3 layers, and can be removed from NFETs without impacting device properties. We thus have achieved sub-100 nm device Vt of 0.3-0.4 V with PFETs Ion ~ 140 muA/mum at Ioff ~13 pA/mum, suitable for low-power technologies. Carrier mobilities are close to those of SiON control devices. Thus the Vt problem impeding the implementation of poly-Si/high-k gate stacks for low power device applications has been resolved

Polymer self assembly in semiconductor microelectronics

Integration of polymer self assembly with semiconductor processing enables sub-lithographic patterning of integrated circuit (IC) device elements and offers a non-traditional pathway to performance improvements (Black, 2005). We discuss target applications including surface-roughening for on-chip decoupling capacitors (Black et al., 2004), patterning nanocrystal floating gates for FLASH devices (Guarini et al., 2003), and defining FET channel arrays (Black, 2005)

Mobility and CMOS devices/circuits on sub-10nm [110] ultra thin body SOI

For the first time, we show the experimental inversion mobility data on ultra thin [110] SOI substrates for thickness as thin as 6nm. Both electron and hole mobility in ultra thin [110] SOI are evaluated as a function of SOI thickness. In addition, novel processes such as [110] selective epitaxy and extremely thin cobalt disilicide CoSi/sub 2/ are developed. Ring oscillators and SRAM cell are demonstrated for the first time on 6nm [110] ultra thin SOI. When compared to ultra thin SOI in (100) substrate, we observe /spl sim/33% drive current enhancement in PFETs at Lg=50nm and /spl sim/1.8X hole mobility enhancement.

Trigate 6T SRAM scaling to 0.06 µm 2

We present an aggressively scaled trigate device architecture with undoped channels, high-k gate dielectric, a single work function metal gate and novel BEOL processing yielding 6T SRAM bit cells as small as 0.06 µm2. This is the smallest SRAM cell demonstrated to date and represents the first time an SRAM based on a multi-gate FET (MUGFET) architecture has surpassed SRAM density scaling demonstrated with planar devices [1].

Very high performance 50 nm CMOS at low temperature

In this work, we present very high performance CMOS devices with 50 nm channel lengths on 1.7 nm gate oxide, suitable for low temperature operation. Saturation transconductances of 1380 mS/mm for nMOSFETs and 523 mS/mm for pMOSFETs are achieved at -200 /spl deg/C. At the same temperature, I/sub on/ for a 1.2 V supply is 1.2 mA//spl mu/m for nMOSFET, and 0.5 mA//spl mu/m for pMOSFET, respectively, with I/sub off/ of both devices on the order of 10 nA//spl mu/m. A delay of 6.4 ps per stage at 1.5 V is measured at -100 /spl deg/C for a 101-stage CMOS ring oscillator. The delay of the same ring oscillator at room temperature is 8.2 ps per stage. These represent the highest CMOS performance figures reported to date.

Patterning of CMOS device structures for 40-80nm pitches and beyond

CMOS device patterning for aggressively scaled pitches (smaller than 80nm pitch) faces many challenges. Maybe one of the most crucial issues during device formation is the pattern transfer from a soft mask (carbon based) material into a hard mask material. A very characteristic phenomenon is that mechanical failure of the soft material may be observed. While this was observed first for patterning below 80nm pitch, it becomes increasingly important for even smaller pitches (≤ 40 nm). Further process optimization by various pre- and post-treatments has enabled robust pattern transfer down to 40nm pitch. A systematic study of the parameters impacting this phenomenon will be shown. Other challenges for patterning devices include profile control and material loss during gate stack patterning and spacer formation. Lastly, initial patterning experiments at an even more aggressive pitch show that the mechanical failure previously observed for larger pitches once again becomes an increasingly important issue to consider.