J. Bock
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Featured researches published by J. Bock.
bipolar/bicmos circuits and technology meeting | 2004
J. Bock; Herbert Schäfer; K. Aufinger; R. Stengl; Sabine Boguth; R. Schreiter; M. Rest; Herbert Knapp; M. Wurzer; Werner Perndl; T. Bottner; T.F. Meister
A SiGe bipolar technology for automotive radar applications around 77 GHz has been developed. A cut-off frequency of 200 GHz, a maximum oscillation frequency of 275 GHz, and a gate delay of 3.5 ps have been obtained. First key building blocks for 77 GHz systems like VCOs and mixers have been realized with this technology.
bipolar/bicmos circuits and technology meeting | 2006
R. K. Vytla; T.F. Meister; K. Aufinger; D. Lukashevich; Sabine Boguth; Herbert Knapp; J. Bock; Herbert Schäfer; Rudolf Lachner
Integration of high voltage transistors and varactors with high tuning range into high frequency SiGe bipolar technologies is challenging due to the requirement of a shallow collector for the high speed transistor. This paper presents a high speed SiGe bipolar technology using a novel concept with two epitaxial layers for the simultaneous integration of high speed transistors, high voltage transistors, and varactors. Using this concept high speed transistors with 209 GHz cut-off frequency and 3.3 ps gate delay have been combined with high voltage transistors providing an emitter-collector breakdown voltage of 5 V. Additionally in this concept a varactor has been developed and optimized to achieve a high tuning range of 13 GHz and low phase noise for a 77 GHz VCO
bipolar/bicmos circuits and technology meeting | 2002
Martin Wurzer; J. Bock; Herbert Knapp; K. Aufinger
A 2:1 static frequency divider fabricated in a 0.35 /spl mu/m SiGe bipolar technology is described. It operates up to 71.8 GHz and draws 132 mA from a single 4.5 V supply. Continuous operation up to the maximum operating frequency of 71.8 GHz has been demonstrated. This operating frequency is the highest achieved for this type of circuit in Si-based technologies and comparable with the fastest static dividers realized in III-V technologies.
bipolar/bicmos circuits and technology meeting | 1998
Martin Wurzer; J. Bock; W. Zirwas; Herbert Knapp; F. Schumann; A. Felder; L. Treitinger
An integrated clock and data recovery circuit (CDR) applying the PLL technique has been developed for future optical transmission systems. It is fabricated in a 0.5 /spl mu/m/50 GHz f/sub T/ double-polysilicon bipolar technology using only production-like process steps. The circuit operates up to 40 Gb/s, which is the highest operating speed to date for this type of IC in a silicon bipolar technology.
IEEE Transactions on Electron Devices | 1996
K. Aufinger; J. Bock; T.F. Meister; J. Popp
The RF noise of transistors fabricated in an advanced silicon bipolar technology is investigated. The influence of the lateral scaling on the noise figure is studied experimentally and compared with the predictions of conventional noise modeling. Reasonable agreement is found without any fitting of model parameters to the measured noise characteristics. The potential of the investigated technology for low-noise applications is demonstrated by noise figures below 1 dB for frequencies up to 2 GHz and below 2 dB up to 7 GHz.
bipolar/bicmos circuits and technology meeting | 2000
Herbert Knapp; J. Bock; M. Wurzer; G. Ritzberger; K. Aufinger; L. Treitinger
Two dual-modulus prescalers manufactured in a low-cost Si bipolar technology are presented. The first circuit is optimized for low power consumption and operates up to 2 GHz at a power consumption of 2 mW. The second prescaler is optimized for high speed and operates up to 12 GHz with a power consumption of 30 mW. The prescalers have selectable divide ratios of 128/129 and 256/257, respectively.
bipolar/bicmos circuits and technology meeting | 2008
Hans-Peter Forstner; H. D. Wohlmuth; Herbert Knapp; C. Gamsjager; J. Bock; T.F. Meister; K. Aufinger
A dielectric resonator oscillator (DRO) based 19 GHz downconverter is presented, which has been integrated in a 200 GHz fT SiGe production technology. The circuits, a negative resistance block and a mixer, have been designed differentially. The DRO is optimized for low phase noise and operates at typically 18 GHz. The mixer converts the by-4-devided signal of a 77 GHz fundamental oscillator to around 1 GHz. Mixer conversion gain is on the order of ntilde 16 dB and the input referred 1 dB compression point is about 0 dBm. Phase Noise of the DRO is ntilde115 dBc/Hz at an offset frequency of 100 kHz. The power dissipation of the complete MMIC is 94 mW, operating off a supply voltage of +5.5 V.
bipolar/bicmos circuits and technology meeting | 2002
G. Ritzberger; Herbert Knapp; J. Bock; K. Aufinger
This paper presents an integrated circuit suitable for frequency synthesis. The circuit consists of a monolithic voltage-controlled oscillator operating up to 30.5 GHz with static divide-by-256/divide-by-257 dual-modulus prescaler and consumes 500 mW from the 5.3 V supply. It is manufactured in a pre-production 0.4 /spl mu/m/85 GHz SiGe bipolar technology.
bipolar/bicmos circuits and technology meeting | 1998
J. Bock; T.F. Meister; H. Knapp; K. Aufinger; Martin Wurzer; R. Gabl; M. Pohl; S. Boguth; M. Franosch; L. Treitinger
A 0.5 /spl mu/m silicon bipolar technology for mixed digital/analogue RF applications is described. Transit frequencies of 51 GHz are achieved using low-energy implantation and subsequent RTP for base doping. A salicide layer serves to reduce base resistance. This enables maximum oscillation frequencies of 60 GHz and 14 ps ECL gate delay at the expense of only one additional mask in comparison to a silicon bipolar production technology.
Electronics Letters | 1999
H. Knapp; H.D. Wohlmuth; J. Bock; Arpad L. Scholtz