Pgm Peter Baltus

A 60 GHz Phase Shifter Integrated With LNA and PA in 65 nm CMOS for Phased Array Systems

This paper presents the design of a 60 GHz phase shifter integrated with a low-noise amplifier (LNA) and power amplifier (PA) in a 65 nm CMOS technology for phased array systems. The 4-bit digitally controlled RF phase shifter is based on programmable weighted combinations of I/Q paths using digitally controlled variable gain amplifiers (VGAs). With the combination of an LNA, a phase shifter and part of a combiner, each receiver path achieves 7.2 dB noise figure, a 360° phase shift range in steps of approximately 22.5°, an average insertion gain of 12 dB at 61 GHz, a 3 dB-bandwidth of 5.5 GHz and dissipates 78 mW. Consisting of a phase shifter and a PA, one transmitter path achieves a maximum output power of higher than +8.3 dBm, a 360° phase shift range in 22.5° steps, an average insertion gain of 7.7 dB at 62 GHz, a 3 dB-bandwidth of 6.5 GHz and dissipates 168 mW.

A 60GHz digitally controlled phase shifter in CMOS

This paper presents a 60 GHz digitally controlled phase shifter in the 65 nm CMOS technology. Using a differential varactor-loaded transmission-line architecture, the phase shifter achieves a phase resolution of 22.5deg, an average insertion loss of 8.5 to 10.3 dB and a return loss of better than 10 dB from 55 to 65 GHz. The phase shifter occupies an area of only 0.2 mm2. To the knowledge of the authors, this is the first 60 GHz digitally controlled phase shifter with a phase resolution of 22.5deg in silicon reported to date. It is well suited for a 60 GHz phased array.

Silicon-Based True-Time-Delay Phased-Array Front-Ends at Ka-Band

A high-power and a low-power fully integrated true-time-delay (TTD) phased-array receiver front-end have been developed for Ka-band applications using a 0.25- μm SiGe:C BiCMOS technology. The high-power front-end, consisting of a high-power low-noise amplifier (LNA) and an active TTD phase shifter, achieves 13.8±1.3 dB gain and a noise figure (NF) below 3.1 dB at 30 GHz. The front-end provides 17.8-ps continuous variable delay, with 3.5% normalized delay variation (NDV) over a 22-37-GHz frequency span. The low-power front-end, composed of a low-power LNA and a passive TTD phase shifter, achieves 14.8±3 dB gain and an NF below 3.2 dB at 30 GHz. The low-power front-end offers 22-ps continuous variable delay with only 5.5% NDV over a 24-40-GHz frequency span. The low-power front-end consumes 22.5-mW power and presents an overall input 1-dB compression point ( P 1 dB) and input third-order intercept point (IIP3) of -22 and -13.8 dBm, respectively. Depending on the linearity requirements, the high-power front-end can operate in dual-power modes. In the high-power (low-power) mode, the measured worst case input P 1 dB and IIP3 are -15.8 ( -18 dBm) and -9 dBm ( -12 dBm) at 30 GHz with an averaged power consumption per channel of 269 mW (111 mW) for similar TTD and gain performance. The core area of the high-power and low-power front-ends are 0.31 and 0.48 mm2, respectively.

Experimental Evaluation of an Adaptive Nonlinear Interference Suppressor for Multimode Transceivers

In multimode transceivers, the transmitter for one communication standard may induce a strong interference in the receiver for another standard. Using linear filtering techniques to suppress this interference requires a receiver with a very large dynamic range, leading to an excessive power consumption. A much more power efficient approach suppresses the interference using an adaptive nonlinear interference suppressor (NIS). In previous work an ideal model was used to derive an adaptation method and study the receiver performance afforded by the NIS. In this paper, we present experimental results of a receiver that uses an implementation of the NIS, fabricated in 140 nm complementary metal-oxide-semiconductor technology. Main imperfections that limit the NIS performance are identified, simple models are developed that explain the experimental results, and for the key imperfections, low-complexity digital compensation and calibration methods are proposed. These digital methods permit the use of lower-performance analogue circuits, thus further reducing the transceiver cost and power consumption. The experimental results show that the NIS can achieve a substantial interference suppression at attractive complexity and power dissipation.

Full MIMO Spatial Filtering Approach for Dynamic Range Reduction in Wideband Cognitive Radios

Wideband cognitive radios (CRs) receive signals from multiple transmitters simultaneously to increase spectrum utilization. Processing a wideband spectrum is challenging due to large dynamic range (DR) of the received signal and required high sampling speed of the ADC. The power consumption of high sampling speed/high-resolution ADCs have been prohibitive for handheld radios. However, in CR applications strong inband signals that pose large DR requirements can be filtered out, since CR needs to detect unused spectrum bands where no signal is present. Spatial domain filtering approaches through use of multiple antennas to reduce DR of the wideband signal are proposed. Algorithms and architectures are developed for vector beamforming (multiple antennas and a single ADC) and full multiple-input multiple-output (MIMO) (multiple antennas with an ADC per antenna) analog spatial filters for adaptive interference suppression. Simulation results indicate that for realistic indoor propagation environments the ADC resolution of an analog beamformer can be reduced by 4 bits when the receiver operates at 2 bits/s/Hz, reducing ADC power consumption by approximately 90%. Moreover, simulations indicate that full MIMO analog spatial filter can reduce ADC resolution with over 3 bits per ADC when the receiver operates at 5 bits/s/Hz, reducing ADC power consumption by approximately 85%.

System study of a 60 GHz wireless-powered monolithic sensor system

State-of-the-art batteryless wireless sensors have separate modules for sensing and energy scavenging. Such separation increases the size and cost of sensors and limits their robustness. To overcome these limitations, we propose a 60 GHz wireless sensor system, which we call the PREMISS system, based on monolithic sensors with on chip sensing, tranceiving, integrated antenna and energy scavenging. In the PREMISS system, a high-power central controller transmits RF energy and information to many low-power low-cost sensors via pencil beams and receive and detect the information from these sensors. In this paper, we present a system study on the PREMISS system highlighting design challenges and practical implementation considerations. From the link budget calculation, we show that in the PREMISS system, a signal to noise ratio of 17 dB at the central controller receiver may be achieved from a sensor 5 meters away. In addition, we also identified that one key challenges in the PREMISS system is the design of good efficiency rectifiers for input power and voltage levels far below those in state-of-the-art 2.4 GHz systems.

2.4GHz energy harvesting for wireless sensor network

This paper presents the analysis of the performance of charge pump, and the design strategy and efficiency optimization of 2.4GHz micro-power charge pump using 65nm CMOS technology. The model of the charge pump takes account of the threshold voltage variation, bulk modulation, and the major parasitic capacitor. Charge pump is sensitive to the input voltage swing and the actual input voltage swing is less after the capacitor divider, which generates the optimized size transistor. From the mathematic model of the charge pump, the relationship between the charge pump performance and design parameter is presented. After parameter analysis and performance discussion, a design procedure to maximize performance is presented. Corresponding to the design procedure presented in this paper, a high efficiency charge pump at 2.4GHz is presented.

A 48–61 GHz LNA in 40-nm CMOS with 3.6 dB minimum NF employing a metal slotting method

This paper presents a low noise amplifier realized in 40-nm CMOS technology for the 60 GHz ISM band. To reduce the noise contribution from the input passive structure, a new metal slotting method is applied to the transmission line for increasing the effective conducting cross-section area. The design incorporates additional noise matching between the common-source stage and the common-gate stage to reduce the noise impact by the latter stage. The measured noise figure is below 4 dB from 51 GHz to 65 GHz, 3.6 dB at 55 GHz and 3.8 dB at 60 GHz. The achieved 3 dB power gain bandwidth is 13 GHz, from 48 GHz to 61 GHz. The peak transducer gain (Gt) is 15 dB at 55 GHz, and 12.5 dB at 60 GHz. The total power consumption is 20.4 mW.

Low voltage comparator for high speed ADC

This paper presents a design of a high-speed, low-voltage, low power consumption comparator with S-R latch for High speed ADC. The comparator is the most important part in the Flash ADC, since the speed and the resolution is determined by the comparator. In this paper, we do the analysis of the traditional comparator and propose a better structure combing sense amplifier and symmetric S-R latch, which can run faster and provide more stable output signal than the traditional structure. The comparator is composed of a latch based amplifier and a S-R latch which provides stable output. There are many issues in the design of the comparator, we will discuss those design issues in this paper.

Systems and Architectures for Very High Frequency Radio Links

This paper discusses very high frequency radio links from the application level down to the circuit constraints. Because of the technical difficulties and higher cost of technologies and packaging, applications at these frequencies only make sense when the special properties of these high frequencies are offering clear advantages for these applications. Such advantages can be higher system capacity, better security and privacy, or higher spatial resolution. Exploiting these advantages requires careful choices in system design and architecture, and imposes specific constraints on circuits and technologies. In most cases, it will also require beam forming through phased array antenna structures. Implementation of the signal processing for beam forming can be achieved in an efficient way in the RF domain.