E Emanuele Lopelli

A FSK demodulator comparison for ultra-low power, low data-rate wireless links in ISM bands

Personal communications require wireless nodes, which can transmit and receive reliably data under huge power constraints. Higher level of integration and reduction of power consumption can be achieved using a zero-IF architecture together with a wideband BFSK modulation scheme. Unfortunately FSK techniques performances degrade sharply in the presence of frequency offset. In this paper a comparison between potentially low power BFSK architectures is presented based on high level models. In depth analysis of four potentially low power demodulators shows that the architecture, which can assure rejection of large static offset with minimum increment in hardware complexity is the ST-DFT based demodulator. This will allow great reduction in power consumption avoiding acquisition and tracking of the offset at the receiver side.

A 1 mA Ultra-Low-Power FHSS TX Front-End Utilizing Direct Modulation With Digital Pre-Distortion

This paper deals with the system and circuit-level aspects of an ultra-low-power robust wireless node for an asymmetric wireless link. A single building block TX front-end for a frequency hopping spread spectrum (FHSS) transmitter implemented in silicon-on-anything (SOA) bipolar technology is presented. It is realized with a directly modulated RF cascoded Colpitts power voltage-controlled oscillator (VCO), a frequency locked loop for center frequency calibration, and a digital pre-distortion algorithm for accurate frequency bins synthesis. The TX front-end draws only 1 mA at -18 dBm output power. By combining digital system techniques for frequency hopping and merging the VCO and the power amplifier (PA), a robust solution is obtained for indoor ultra-low-power wireless links. The proposed pre-distortion concept allows reduction of the hardware complexity, while the combination of a cascode output buffer and a common-collector Colpitts VCO allows us to reduce the complete FHSS front-end to a single building block that directly drives the antenna through a balun. A dedicated digital algorithm on the receiver side reduces the center frequency offset from a maximum value of 8.2 MHz to less than 8 ppm avoiding the use of any crystal on the transmitter side. Precision in the hopping synthesis is obtained by employing a ST-DFT based demodulator with differential encoding and an offset sending technique. The novel FHSS-predistortion concept has been verified by realizing a full wireless link that achieves a bit error rate better than 1.1% at -25 dBm output power while transmitting across an 8 meters indoor non-line-of-sight (NLOS) path.

Minimum Power-Consumption Estimation in ROM-Based DDFS for Frequency-Hopping Ultralow-Power Transmitters

The future of all kinds of applications that require a submilliwatt consumption strictly depends on the capability to meet design specifications at the minimum power costs. While several computer-aided-design tools are present to estimate the power consumption of modern ICs at transistor level, it is very difficult to predict the power at higher level. Given the reduced time-to-market of modern communication devices, it is very often needed to have accurate power estimations prior to the transistor-level design. Allocating a too conservative power budget to a block implies a possible poor tradeoff between the specifications of building blocks that constitute the system and their power consumption. For future power-constrained wireless devices (like wireless nodes in sensor networks), it is very important to have high-level models which can help the designer with the initial high-level choices without going into transistor-level design. One of the important blocks in modern communication devices, particularly for spread-spectrum systems, is the frequency synthesizer. In this paper, the first power-consumption model for an ultralow-power ROM-based direct digital frequency synthesizer has been developed, which can help the designer in the power optimization at a high level prior to transistor implementation.

ULTRA-LOW POWER FREQUENCY-HOPPING SPREAD SPECTRUM TRANSMITTERS AND RECEIVERS

This paper examines system and circuit design techniques for a “microWatt node” operating at power level low enough to enable the use of an energy scavenging source. While several architectures have been investigated in order to reduce the overall system power consumption, none of them is able to guarantee robustness of the link and ultra-low power consumption at the same time. A survey of the most advanced architectures meant for ultra-low power transceivers is described. Advantages and drawbacks of all these systems are discussed and the reasons for an architecture based on Frequency-Hopping (FH) Spread-Spectrum (SS) are discussed. Finally a novel FH synthesizer based on digital pre-distortion architecture is proposed in order to reduce the power consumption of the hopping synthesizer. The FH architecture together with a frequency offset robust demodulation technique allows a reduction by a factor 8 of the power consumption compared to the state-of-the-art synthesizers. Furthermore, a single RF block front-end is obtained combining together the VCO and the PA. The novel RF front-end can be directly coupled to the antenna through a balun and the system is able to deliver -18 dBm output power on 50 Ω load at 1 mA current consumption (2 V power supply). To prove the new synthesizer principle a communication link in the 902-928 MHz ISM band has been set-up. The receiver, mainly software with a flexible RF front-end, adopted a ST-DFT demodulation algorithm and achieved a BER smaller than 1.1% at -25 dBm output power, with TX and RX antennas placed at 8 meters distance in a NLOS condition and in a common office environment.

An ultra-low power predistortion-based FHSS transmitter

In the new era of personal communications, the energy available for a wireless node is the limiting factor. Furthermore wireless links should be robust even in the harsh indoor environment where fading, attenuation and interferences can be severe. Spread-spectrum techniques are largely used to have a robust link, while frequency-hopping (FH) is the most suitable for low data-rate applications. Unfortunately state-of-the-art FH systems are still far too complex and too power hungry to be implemented in a self contained wireless node. The proposed architecture simplifies considerably the hardware requirements for the hopping synthesizer achieving a current consumption of only 900 muA (excluding the output buffer) from a 1.8 V power supply

A sub-mA FH frequency synthesizer technique

A novel frequency-hopping spread-spectrum transmitter architecture is presented that provides robust communications in the 915 MHz ISM band while dissipating very low power. The frequency-hopping front-end consists of a VCO, dividers and output stage. A base-band predistortion algorithm allows hopping with minimum hardware complexity. The TX front-end has been fabricated in silicon-on-anything (SOA) bipolar technology and a BFSK modulated wireless link using a dedicated receiver has been realized. A 1kbps, 1khop/s link with a BER smaller than 1.1 % has been achieved at -25 dBm output power while having 64 orthogonal channels. The synthesizer architecture (VCO+divider+base-band) dissipates only 870mA

A Frequency Offset Recovery Algorithm for Crystal-Less Transmitters

In the growing market of low-cost, low data-rate wireless applications there is a significant motivation to implement crystal-less wireless nodes, which reduces costs and form factor. Several applications benefit from an asymmetric wireless scenario in which the transmitter is required to be cheap, small and ultra-low power, while the receiver is a residential gateway (RG) or a base-station with a virtually unlimited power budget and relatively higher allowable cost and form factor. In this scenario, while the transmitter is implemented as a crystal-less node, all the required complexity in the frequency synchronization can be shifted to the RG. Nevertheless the acquisition time should be short compared to the transmission time to save power in the transmitter, and frequency offset in the MHz range should be reduced to few kHz. A new algorithm, which can easily recover frequency offsets larger than the data-rate and which can address the aforementioned issues, is proposed in this paper

A 0.75V 325µW 40dB-SFDR frequency-hopping synthesizer for wireless sensor networks in 90nm CMOS

A limitation in the use of Frequency-Hopping Spread Spectrum (FHSS) for ultra-low-power Wireless Sensor Networks (WSNs) is the power dissipation of existing solutions. Whereas FHSS would make WSNs very robust and secure in difficult fading (indoor) environments, state-of-the-art solutions based on PLLs and digital frequency synthesizers require supply currents of several milliamperes [1,2]. A solution that consumes significantly less than 1mA is required to enable FHSS in autonomous WSN nodes. Power dissipation should also be independent of the hopping speed, as fast frequency hopping allows for fast synchronization, and results in minimum power overhead in the WSN. Furthermore, a fast hopping speed without power penalty allows designers to reduce the transmitted SNR by trading off hopping speed for transmitted power.

Architectures and synthesizers for ultra-low power fast frequency-hopping WSN radios

1 Introduction. 1.1 Application field. 1.2 System requirements. 1.3 Energy scavenging techniques. 1.4 General wireless node requirements. 1.5 State of the art. 1.6 The objectives of this book. 1.7 Outline of the book. 2 System-Level and Architectural Trade-offs. 2.1 Modulation schemes for ultra-low power wireless nodes. 2.2 Optimal Data-rate. 2.3 Transmitter architectures. 2.4 Receiver architectures. 2.5 Conclusions. 3 FHSS Systems: State-of-the-art and Power Trade-offs. 3.1 Synchronization. 3.2 State-of-the-art Frequency Hopping Spread Spectrum (FHSS) systems. 3.3 Frequency Hopping (FH) synthesizer architectures. 3.4 Specifications for ultra-low-power frequency-hopping synthesizers. 3.5 PLL power estimation model. 3.6 Direct Digital Frequency Synthesizer (DDFS) power estimation model. 3.7 Summarizing discussion. 3.8 Conclusions. 4 A One-way Link Transceiver Design. 4.1 General guidelines for transmitter design. 4.2 Transmitter architecture. 4.3 Receiver architecture. 4.4 Implementation and experimental results. 4.5 Conclusions. 5 A Two-way Link Transceiver Design. 5.1 Transmitter design general guidelines. 5.2 Transmitter architecture. 5.3 Synthesizer design. 5.4 Generation of a 288-MHz reference clock. 5.5 Receiver design at system level. 5.6 Simulation and experimental results. 5.7 Conclusions. 6 Summary and conclusions. 7 Acronyms. Appendices. A Walsh based harmonic rejection sensitivity analysis. References.