Arjan Leeuwenburgh

A low-voltage folded-switching mixer in 0.18-/spl mu/m CMOS

Scaling of CMOS technologies has a great impact on analog design. The most severe consequence is the reduction of the voltage supply. In this paper, a low voltage, low power, AC-coupled folded-switching mixer with current-reuse is presented. The main advantages of the introduced mixer topology are: high voltage gain, moderate noise figure, moderate linearity, and operation at low supply voltages. Insight into the mixer operation is given by analyzing voltage gain, noise figure (NF), linearity (IIP3), and DC stability. The mixer is designed and implemented in 0.18-/spl mu/m CMOS technology with metal-insulator-metal (MIM) capacitors as an option. The active chip area is 160 /spl mu/m/spl times/200 /spl mu/m. At 2.4 GHz a single side band (SSB) noise figure of 13.9 dB, a voltage gain of 11.9 dB and an IIP3 of -3 dBm are measured at a supply voltage of 1 V and with a power consumption of only 3.2 mW. At a supply voltage of 1.8 V, an SSB noise figure of 12.9 dB, a voltage gain of 16 dB and an IIP3 of 1 dBm are measured at a power consumption of 8.1 mW.

Fully-integrated DECT/Bluetooth multi-band LNA in 0.18 /spl mu/m CMOS

The design of a multi-band low noise amplifier (LNA) is the first obstacle towards the design of a multi-standard receiver. In this paper, an approach for the design of a multi-band LNA for DECT and Bluetooth is presented. The formula for a minimal noise factor of a LNA, that takes into account the finite quality factor of the inductors is derived and the full design procedure that facilitates the design of a fully integrated LNA is given. The main advantages of the presented multi-band LNA are: high level of integration, reduced chip area by using only one integrated inductor, while the other is implemented as a bond-wire, input matching at two frequencies while having low noise figure, moderate voltage gain and good linearity. In DECT mode the simulated LNA performance is: NF = 2.2 dB, gain = 17 dB, IIP3 = 0.5 dBm, with a current of 8 mA, while in Bluetooth mode the LNA achieves: NF = 2.3 dB, gain = 15 dB, IIP3 = 3 dBm, with a current of only 4 mA.

A high gain, low voltage folded-switching mixer with current-reuse in 0.18 /spl mu/m CMOS

The scaling of CMOS technologies has a great impact on analog design. The most severe consequence is a reduction of the voltage supply. In this article, a new low voltage folded-switching mixer with current reuse, which operates at 1 V supply voltage, is discussed. The main advantages of the introduced mixer topology are: a high voltage gain, a moderate noise figure and an operation at low supply voltages. Full insight into mixer operation is given by analyzing voltage gain, noise figure, linearity (IIP3) and DC stability. The mixer is designed and implemented in 0.18 /spl mu/m CMOS technology with MIM capacitors as an option. The active chip area is 160 /spl mu/m/spl times/200 /spl mu/m. At 2.4 GHz, a single side band (SSB) noise figure of 13.9 dB, a voltage gain of 11.9 dB and IIP3 of -3 dBm are measured at a supply voltage of 1 V and with a power consumption of 3.2 mW.

Low voltage, low power folded-switching mixer with current-reuse in 0.18 /spl mu/m CMOS

The scaling of the CMOS technologies has a great impact on analog design. The most severe consequence is a reduction of the voltage supply. In this article, a new low-voltage folded-switching mixer with current-reuse, which operates at 1 V supply voltage, is discussed. The main advantages of the introduced mixer topology are: a high voltage gain, a low noise figure, an operation at low supply voltages and flexibility in terms of mixer redesign for operation at different supply voltages. In order to alleviate the mixer design for different set of specifications and to provide a designer with a mixer design procedure, insight into mixer operation is given analyzing gain, noise figure and linearity. The mixer is designed in 0.18 /spl mu/m CMOS technology. Taking into account the obtained simulation results at a supply voltage of 1 V (gain = 9 dB, NF = 12 dB, IIP3 = -1 dBm) and with a power consumption of 2.8 mW, the presented folded-switching mixer with current-reuse outperforms many of, so far, published CMOS mixers.

Adaptive multi-standard RF front-ends

Glossary. Abbreviations. 1 Introduction. 1.1 The state-of-the-art in multi-standard RF transceivers. 1.2 Scope. 1.3 Outline. 2 Front-end architecture selection. 2.1 A generic front-end architecture. 2.2 A set of front-end architectures. 2.3 Selection criteria. 2.4 Selection of a suitable front-end architecture. 2.5 Summary. 3 Broad-band polyphase filters. 3.1 Passive polyphase filter topology. 3.2 RC polyphase filters and their applications. 3.3 Design considerations. 3.4 Summary. 4 Analysis of low-IF architectures. 4.1 Noise and voltage gain analysis in a low-IF front-end. 4.2 Linearity analysis. 4.3 Image rejection analysis. 4.4 Summary. 5 RF and building block specifications. 5.1 RF specifications. 5.2 Distribution of building block specifications. 5.3 Summary. 6 A low-voltage folded switching mixer. 6.1 Transconductors for folded switching mixers. 6.2 AC-coupled folded switching mixer with current-reuse. 6.3 Simulation and experimental results. 6.4 Mixer benchmarking. 6.5 Summary. 7 Multi-band reconfigurable complex mixer. 7.1 1.9 - 2.4 GHz reconfigurable complex mixer. 7.2 1.9 - 2.4 GHz conventional complex mixer. 7.3 Summary. 8 Reconfigurable multi-band LNA. 8.1 Design considerations. 8.2 Design procedure. 8.3 Design example. 8.4 A reconfigurable multi-band DECT/Bluetooth LNA. 8.5 Summary. 9 Reconfigurable multi-band RF front-end. 10 Conclusions. A RF, system and bulding block specifications. B Noise factor of a two-port network. C Noise factor of a passive RF block. References.

Mixer topology selection for a 1.8 - 2.5 GHz multi-standard front-end in 0.18 /spl mu/m CMOS

In this paper the selection of a mixer topology for a multi-standard, non-concurrent front-end is presented. The front-end is designed for Digital Enhanced Cordless Telephone (DECT) systems and systems for wireless communications, which operate in the 2.4 GHz Industrial Scientific Medical (ISM) band (like Bluetooth or DECT alike systems at 2.4 GHz). Three mixer topologies are presented and evaluated. In order to choose the most promising one, a figure of merit for mixers is defined. A novel, folded switching mixer topology utilizing a current reuse technique achieves the best performance. With this topology the following simulation results are achieved: noise figure (NF) 11 dB, voltage gain 17 dB, linearity (IIP/sub 3/) 1 dBm with a power consumption of 5 mW at an operating frequency of 2.5 GHz. Given the fast migration of the CMOS technologies towards the deep submicron processes, mixer operation at low supply voltages is considered. The operation at a supply voltage of 1 V providing moderate NF, gain and linearity for two mixer topologies is shown, which is not reported in the literature so far.

Analysis of an 1.8 - 2.5 GHz multi-standard high image-reject front-end

In this paper, the analysis of a multi-standard, high image-reject front-end is presented. The front-end is designed to be used for Digital European Cordless Telephone (DECT) systems and wireless communications systems, which operate in the 2.4 GHz Industrial Scientific Medical (ISM) band (like Bluetooth). A double-quadrature low-IF architecture is chosen, because it can provide a high image rejection ratio (IRR) and a flexibility in terms of different systems. In the selected architecture, an RC polyphase filter is applied as an RF I/Q generator. Building block specifications are optimized in order to achieve two goals: a high IRR and a high sensitivity of the receiver. Assuming a mismatch of 1% between the elements of the RC polyphase filter and 2/spl deg/ phase mismatch in the local oscillator path, a simulated IRR of 63 dB is obtained in the frequency range 1.8 - 2.5 GHz. In spite of the fact that the RC polyphase filter deteriorates the front-end noise figure (NF), a NF of 6 dB and a sensitivity of -93 dBm for the DECT receiver has been achieved.

A DECT/Bluetooth multi-standard front-end with adaptive image rejection in 0.18 /spl mu/m CMOS

A DECT/Bluetooth multi-standard front-end with adaptive image rejection is described. The front-end is designed and simulated in 0.18 /spl mu/m CMOS technology. Using a multi-band LNA with zero external components full integration of the front-end is achieved. In high image-reject DECT mode it has a NF of 10 dB consuming a current of 47 mA, while in low image-reject DECT mode a NF of 5 dB is obtained with a current of 39 mA. In high image-reject Bluetooth mode the front-end achieves a NF of 10 dB consuming a current of 39 mA and in low image-reject Bluetooth mode it has a NF of 5 dB using a current of 31 mA. Applying adaptive image rejection the power consumption is reduced 20%, the NF is improved 50% and the gain improves 30%, while the chip area is negligibly increased compared to the total chip area occupied by the front-end.