Johan van der Cingel

VUV/Low-Energy Electron Si Photodiodes With Postmetal 400

Pure boron (PureB) chemical-vapor deposition performed at 400°C is applied as a postmetalization process module to fabricate near-ideal p+n photodiodes with nm-thin PureB-only beam-entrance windows. The photodiodes have near-theoretical sensitivity and high stability for optical characterization performed with either UV light down to a wavelength of 270 nm or low-energy electrons down to 200 eV.

^{\circ}{\rm C}

In this study, we successfully achieved a relatively high field-effect mobility of 37.7 cm2/Vs in an InZnO thin-film transistor (TFT) fabricated by excimer layer annealing (ELA). The ELA process allowed us to fabricate such a high-performance InZnO TFT at the substrate temperature less than 50 °C according to thermal calculation. Our analysis revealed that high-energy irradiation in ELA produced a mixed phase of InZnO and SiO2, leading to the deterioration of TFT characteristics.

PureB Deposition

For the application of carbon nanotubes (CNT) as interconnects in integrated circuits low temperature vertically aligned growth with a high tube density is required. We found that etching and cleaning steps used in semiconductor technology can damage the catalyst or support layer, preventing low temperature aligned CNT growth. We propose to use a lift-off process and sacrificial layer to prevent damage. Using this method we created low temperature electrical measurement structures for CNT bundles. The bundles grown at 500 °C display a low resistivity and good Ohmic contact. Finally, we demonstrate that CNT can be covered by PECVD silicon oxide and nitride without inducing damage, which is of interest for low temperature bottom-up integration.

Low temperature high-mobility InZnO thin-film transistors fabricated by excimer laser annealing

Vertical stacking of transistors is a promising technology which can realize compact and high-speed integrated circuits (ICs) with a short interconnect delay and increased functionality. Two layers of low-temperature fabricated single-grain thin-film transistors (SG TFTs) have been monolithically integrated. Using a finite element method (FEM) simulation, the damage to the bottom layer devices during laser crystallization of the top layer silicon layer has been investigated. N-channel metal–oxide–semiconductor (n-MOS) mobilities are 565 and 393 cm2 V-1 s-1 and p-channel MOS (p-MOS) mobilities are 159 and 141 cm2 V-1 s-1, for the top and bottom layers respectively. A three-dimensional (3D) complementary MOS (CMOS) inverter has also been fabricated, with one transistor on the bottom layer and the other on the top layer.

Integrating low temperature aligned carbon nanotubes as vertical interconnects in Si technology

Carbon nanotubes (CNT) can be an attractive candidate for vertical interconnects due to their bottom-up nature and excellent electrical and thermal properties. In this paper we demonstrate low temperature high-density CNT growth and results of electrical characterization. We determined that our CNT contact resistance is low compared to other results in literature, likely caused by a good top contact. The CNT display good uniformity over the wafer and the calculated resistivity of 10 mΩ-cm is among the lowest in literature.

Stacking of Single-Grain Thin-Film Transistors

Carbon nanotubes (CNT) can be an attractive candidate for vertical interconnects (vias) in three-dimensional integrated circuits due to their excellent thermal and electrical properties. To investigate the electrical resistivity of CNT, test vias were fabricated using both a top-down and bottom-up approach. The measured resistivity for the top-down process of 10 mΩ cm is among the better values found in literature. Beside this, the ability to grow CNT directly on single-grain thin-film transistors (SG-TFT) was demonstrated. The electrical performance of the SG-TFT was found not to be influenced by the CNT growth.

Electrical characterization of carbon nanotube vertical interconnects with different lengths and widths

Carbon nanotubes (CNT) can be an attractive candidate for vertical interconnects in 3D monolithic integration, due to their excellent thermal and electrical properties. In this paper we investigate the use of a true bottom-up approach to fabricate CNT vias, for application in 3D monolithic integration. This circumvents metal deposition in high aspect ratio holes, and also allows the use of bundle densification techniques to increase CNT density. Using this approach we fabricated four-point probe electrical measurement structures for both as-grown and densified CNT bundles, and performed I-V measurements. The resulting I-V curves display non-linearities due to a non-Ohmic top contact. The measured resistivities of 10-20 mΩ-cm are among the better values found in literature.

Towards the Integration of Carbon Nanotubes as Vias in Monolithic Three-Dimensional Integrated Circuits

We report high performance (100) and (110) oriented single-grain thin-film-transistors (SG-TFTs) fabricated below 600°C without any seed substrate. The orientation has been contolled by ¼-Czochralski process with the excimer laser. Field-effect mobility of n-channel transistor is 998cm²/Vs for (100) SG-TFTs and 811cm²/Vs for (110) SG-TFTs. Field-effect mobility of p-channel transistor is 292cm²/Vs for (100) SG-TFT and 429cm²/Vs for (110) SG-TFTs.

Low-temperature bottom-up integration of carbon nanotubes for vertical interconnects in monolithic 3D integrated circuits

Integration and properties of devices processed by excimer laser annealing are presented. The best results are achieved by shallow implantations into a native-oxide-free silicon surface and laser annealing with the remainder of the device protected by an Al reflective layer. Low-temperature MISFETs are fabricated with a metal-gate high-k gate stack of PECVD SiO2 and ALD Al2O3 with an EOT of 9.2 nm and an Al-gate. The source/drain regions are self-aligned to the metal gate, which also serves as a laser masking reflective layer. Ablation of the masking layer is prevented due to the low thermal resistance of the thin underlying gate dielectric. The measured devices exhibit good current drivability, which improves with higher laser energy. The maximum processing temperature of the presented MISFETs is 400°C and can potentially to be reduced down to 300°C.

Integrated high performance (100) and (110) oriented single-grain Si TFTs without seed substrate

We report high performance single-grain Ge TFTs by μ-Czochralski process. Electron mobilites are 3337cm²/Vs with on/off ratio of 10⁸ @V<inf>DS</inf>=0.1V. Hole mobilities are 1719cm²/Vs with on/off ratio of 10⁸ @V<inf>DS</inf>=0.05V. The high mobility is due to improved interface property and tensile stress.