J. M. García del Pozo

A Novel CMOS Envelope Detector Structure

A novel high performance envelope detector is offered in this work. Proposed circuit holds the signal peaks in two periods and combines them to obtain the envelope of the signal. This way, ripple is fixed by the peak holder and tracking can be improved without the traditional compensation between keeping and tracking required in these circuits. A comparison is offered between a conventional circuit, a previous work and the proposed envelope detector. It is shown the superior performance of the latter obtaining small ripple (<1%), fast settling (0.4mus) and high linearity.

Low-voltage CMOS variable preamplifier for fiber-based gigabit ethernet

In this paper we present a low-voltage preamplifier destined for optical-fiber communication front-ends in the standard Gigabit Ethernet. Designed in a low-cost 0.35 μm CMOS technology, the circuit can work with a single 1.8 V supply voltage, consumes only 6.2 mW and exhibits a tunable transimpedance from 50 to 65 dBΩ with bit rates up to 1.5 Gb/s.

Broadband linearly tunable CMOS transconductor

A 2.2-V positive variable CMOS transconductor designed in a low-cost 0.35 μm CMOS digital process intended for wideband applications is presented. The cell achieves in worst cases 1.5 mS, 2 GHz and a total noise contribution of 1.45 μArms. The circuit presents high linearity, thanks to the use of the parallel connection between two NMOS transistors, one working in the saturation region and the other in the triode region. Models for different key responses are provided and compared with simulation results.

10GBase-LX4 limiting amplifier in 0.18 µm CMOS digital process with tunable shunt-peaking

This work introduces a monolithic 10GBase-LX4 limiting amplifier in a low-cost 0.18 µm CMOS digital process intended for optical fiber communications. The proposed configuration includes two inductorless frequency compensated voltage amplifiers. The topology also incorporates a conventional RC network in order to avoid drifts due to matching and temperature between −20 and 80 °C. This circuit presents a 200 kHz lower cut-off frequency and a 3.5 GHz higher cut-off frequency with 32 dB gain.

Improved 10GBase-LX4 Limiting Amplifier in a Low-Cost 0.18 μm CMOS Technology

This work overcomes the limitations of a previous work by using three high frequency compensation techniques: polezero cancellation, shunt-peaking and downscaling. By considering these strategies, a fully integrated limiting amplifier in a low-cost 0.18 μm CMOS digital process is introduced. This design improves the original design without inductors and without local multi-feedback loops obtaining a compact, stable and robust design perfectly intended for low-voltage applications.

CMOS optical receiver for 10 Gigabit Ethernet

This paper describes a receiver suitable for 10 Gigabit Ethernet fiber optical networks in the standard LX4. Designed in low-cost CMOS 0.18 mum digital technology, the system is based on CMOS actively loaded inverter structures and works with a single 1.8 V supply voltage. The changes in the operating points due to temperature are minimized between -20 and 80degC by using two compensation techniques. The system presents optimized area and power consumption achieving good trade-off between all important magnitudes.