N. Medrano

An Ultralow-Power Low-Voltage Class-AB Fully Differential OpAmp for Long-Life Autonomous Portable Equipment

This brief presents an ultralow-power class-AB operational amplifier (OpAmp) designed in a low-cost 0.18- μm CMOS technology. The proposed circuit uses transistors biased in the subthreshold region for low-voltage low-power operation. For a 0.8-V single supply, this OpAmp has 51-dB open-loop gain, 57-kHz unity-gain frequency, 60° phase margin, and 65-dB common-mode rejection ratio for 8-pF loads with a power consumption of only 1.2 μW. Experimental results illustrate performances such as a 0.14-V/μs slew rate and a 750-mV linear output swing, demonstrating its correct functionality.

12-b Enhanced Input Range On-Chip Quasi-Digital Converter With Temperature Compensation

This brief presents a monolithic 1.8-V 0.18-μm CMOS temperature-compensated voltage-to-frequency converter for sensor read-out interfaces in wireless sensor network applications. Measurement results show that the proposed converter features are suitable for an output frequency span of 2 MHz with an input voltage range of 0.1-1.6 V. This converter presents a relative error below 4.8% and a linearity error below 0.017% (i.e., 12 b) over the whole frequency span for a range of ( -40°C, + 85°C). Power consumption is 0.423 mW (20 nW in sleep mode), and it occupies an active area of 137 μm x 100 μm.

Square-Signal-Based Algorithm for Analog Lock-In Amplifiers

Dual-phase lock-in amplifiers (LIAs) are designed to extract information (amplitude and phase) from signals buried in high noise levels. In spite of their popularity, their use has been traditionally limited to input sinusoidal waves with symmetric power supplies. This paper presents an algorithm that enables single-supply analog LIAs to properly process input square waves. Formed by linear equations, its computational implementation is much simpler than that of the traditional sinusoidal algorithm. Moreover, applied to battery-operated microcontrolled systems where square signals can be generated by the embedded microcontroller, it presents intrinsic advantages such as simplicity, versatility, and reduction in power and size. Experimental results validate the proposed algorithm, confirming its enormous possibilities in sensing applications.

Low-Voltage Low-Power CMOS Rail-to-Rail Voltage-to-Current Converters

This paper presents three compact CMOS voltage-to-current converters based on OTA/common-source configurations, which attain rail-to-rail input-output operation. The three converters present a high impedance input node while provide a highly linear V-I relationship over a ( -40, +120°C) temperature range with a maximum transconductance temperature coefficient of 175 ppm/°C. Measurement results for 1.2-V 0.18- μm CMOS implementations confirm rail-to-rail operation with bandwidths of up to 14.5 MHz and THD of up to -50 dB for 1 Vpp at 100 kHz, active areas below 0.0145 μm2 and power consumption below 85 μW, which make these basic building blocks suitable for portable applications.

Designing Adaptive Conditioning Electronics for Smart Sensing

This paper presents a robust digitally programmable CMOS analogue processor designed for sensor output conditioning in embedded applications. In addition, system adaptability allows for correction of the deviations in circuit operation due to ageing, mismatch or environmental effects, lending a smart nature to the devices. In order to tune the free parameters of the system, two training strategies based on perturbative algorithms are compared. The processor performance is validated by adjusting the response of an angular position sensor and the insensitivity to parameter mismatch is demonstrated through high-level simulations based on Monte Carlo electrical simulation data.

A low-power high-sensitivity CMOS voltage-to-frequency converter

This paper presents a low-cost high-speed CMOS voltage-to-frequency converter (VFC) which targets front-end sensor interfacing in wireless sensor networks applications. The proposed VFC, designed in a 0.35 µm CMOS technology supplied at 3 V, is very simple, obtaining at the same time high performance characteristics: it operates with a power consumption below 1.03 mW at output frequencies ranging from 1.198 MHz to 2.186 MHz given a 1.0–2.0 V input (1 MHz/V sensitivity) with an accuracy better than 1 %.

A High Performance LIA-Based Interface for Battery Powered Sensing Devices.

This paper proposes a battery-compatible electronic interface based on a general purpose lock-in amplifier (LIA) capable of recovering input signals up to the MHz range. The core is a novel ASIC fabricated in 1.8 V 0.18 µm CMOS technology, which contains a dual-phase analog lock-in amplifier consisting of carefully designed building blocks to allow configurability over a wide frequency range while maintaining low power consumption. It operates using square input signals. Hence, for battery-operated microcontrolled systems, where square reference and exciting signals can be generated by the embedded microcontroller, the system benefits from intrinsic advantages such as simplicity, versatility and reduction in power and size. Experimental results confirm the signal recovery capability with signal-to-noise power ratios down to −39 dB with relative errors below 0.07% up to 1 MHz. Furthermore, the system has been successfully tested measuring the response of a microcantilever-based resonant sensor, achieving similar results with better power-bandwidth trade-off compared to other LIAs based on commercial off-the-shelf (COTS) components and commercial LIA equipment.

An ultra low-power low-voltage class AB CMOS fully differential OpAmp

This paper presents an ultra low-power class AB operational amplifier (OpAmp) designed in a low-cost 0.18 μm CMOS technology. Rail-to-rail input operation is achieved by using complementary input pairs with adaptive bias to enhance slew-rate. A class AB output stage is employed. For low-voltage low-power operation, the transistors both in the input and the output stage are biased in the sub-threshold region. The simulated DC open loop gain is 51 dB, the unity gain frequency is 40 kHz with a 65° phase margin and the slew-rate is 0.12 V/μs with 10 pF capacitive loads. A common-mode feed-forward circuit (CMFF) increases CMRR, keeping the DC gain almost constant: its relative error remains below 1 % for a (-40°C, +120°C) temperature range. The proposed OpAmp consumes only 1 μW at 0.8 V supply.

CMOS Voltage-to-Frequency Converter With Temperature Drift Compensation

This paper presents a new complementary metal-oxide-semiconductor (CMOS) differential voltage-to-frequency converter (VFC) suitable for sensor signal conditioning. Designed in a low-cost 0.18- μm CMOS process, the proposed VFC consumes less than 0.4 mW at a 1.8-V supply. For a differential input range of 0-1.2 V, output frequency varies from 0.1 to 1.1 MHz with a linearity error of less than 0.4%. A new temperature compensation technique keeps the gain error below 2.4% over the whole frequency span for a range of -20°C- +120°C.

Precision CMOS current reference with process and temperature compensation

This paper presents a new first-order temperature compensated CMOS current reference. To achieve a compact architecture able to operate under low voltage with low power consumption, it is based on a self-biasing beta multiplier current generator. Compensation against temperature is achieved by using instead of an ordinary resistor two triode transistors in parallel, acting as a negative and a positive temperature coefficient resistor, that generate a proportional to absolute temperature and a complementary to absolute temperature current which can be directly added to attain a temperature compensated current. Programmability is included to adjust the temperature coefficient and the reference current magnitude over process variations. Results for a 0.18 μm CMOS implementation show that the proposed 500 nA reference operate with supplies down to 1.2 V accomplishing over a (-40 to +120°C) range temperature drifts below 120 ppm/°C.