J. P. Alegre

Low-Voltage Linearly Tunable CMOS Transconductor With Common-Mode Feedforward

This paper presents a new low-voltage pseudodifferential continuous-time CMOS transconductor for wide-band applications. The proposed cell is based on a feedforward cancellation of the input common-mode signal and keeps the input common mode voltage constant, while the transconductance is easily tunable through a continuous bias voltage. Linearity is preserved during the tuning process for a moderate range of transconductance values. Measurements results for a 0.35-m CMOS design show a 1:2 tuning range with total harmonic distortion figures at 10 MHz below 58 dB over the whole range up to a 200- differential output current. The proposed cell consumes less than 1.1 mW from a single 1.8-V supply.

SiGe Analog AGC Circuit for an 802.11a WLAN Direct Conversion Receiver

This brief presents a baseband automatic gain control (AGC) circuit for an IEEE 802.11a wireless local area network (WLAN) direct conversion receiver. The whole receiver is to be fully integrated in a low-cost 0.25- mum 75-GHz SiGe bipolar complementary metal-oxide-semiconductor (BiCMOS) process; thus, the AGC has been implemented in this technology by employing newly designed cells, such as a linear variable gain amplifier (VGA) and a fast-settling peak detector. Due to the stringent settling-time constraints of this system, a feedforward gain control architecture is proposed to achieve fast convergence. The proposed AGC is composed of two coarse-gain stages and a fine-gain stage, with a feedforward control loop for each stage. It converges with a gain error of below plusmn1 dB in less than 3.2 mus, whereas the power and area consumption are 13.75 mW and 0.225 mm2 , respectively.

Design of a Novel Envelope Detector for Fast-Settling Circuits

A novel envelope detector structure that overcomes the traditional tradeoff required in these circuits, improving both the tracking and keeping of the signal, which is specially advantageous for fast-settling circuits, is proposed in this paper. The method relies on holding the signal by two capacitors in parallel, discharging one when the other is in the hold mode and employing the held signals to form the output. Results show a savings greater than 60% of the capacitor area for the same ripple ( < 1%) and a release time constant that is 13 times smaller than that obtained by conventional circuits.

A fast compact CMOS feedforward automatic gain control circuit

This paper presents a fast settling compact feedforward automatic gain control (AGC) suitable for use in wireless communication systems such as WLAN or Bluetooth receivers where the use of traditional closed loop feedback amplifiers forms a boundary due to the stringent settling time constraints. The AGC has been implemented in a 0.35 mum standard CMOS technology. Supplied at 1.8 V, it operates with a power consumption of 1.6 mW at frequencies as high as 100 MHz, while its gain ranges from 0 to 18 dB. The settling time of the circuit is below 0.25 mus.

A high performance CMOS feedforward AGC circuit for wideband wireless receivers

This paper presents a fast settling compact feedforward automatic gain control (AGC) suitable for use in wireless communication systems such as WLAN or Bluetooth receivers where the use of traditional closed loop feedback amplifiers forms a boundary due to the stringent settling time constraints. The AGC has been implemented in a 0.35 mum standard CMOS technology. Supplied at 1.8 V, it operates with a power consumption of 1.6 mW at frequencies as high as 100 MHz, while its gain ranges from 0 to 21 dB in 3 dB steps through a 4-bit word. The settling time of the circuit is below 0.25 mus.

Low-Voltage Linearly Tunable CMOS Transconductor with Common-Mode Feedforward

This paper presents a new low-voltage pseudo-differential continuous-time CMOS transconductor for wideband applications. The proposed cell is based on a feedforward cancellation of the input common-mode signal and keeps the input common mode voltage constant, while the transconductance is easily tunable through a continuous bias voltage. Linearity is preserved during the tuning process for a moderate range of transconductance values. Simulation results for a 0.35 mum CMOS design show a 1:2 Gm tuning range with an almost constant bandwidth over 600 MHz. Total harmonic distortion figures are below -60 dB over the whole range at 10 MHz up to a 200 muAp-p differential output. The proposed cell consumes less than 1.2 mW from a single 2.0 V supply

A Low-Ripple Fast-Settling CMOS Envelope Detector

The design of a high performance envelope detector is made in this work. Proposed circuit does not need the traditional compensation between keeping and tracking required in these circuits due to a system by what the signal peaks are held in two periods and combined to obtain the envelope of the signal. Simulation results are offered comparing both the conventional and the proposed envelope detector and it is shown the superior performance of this circuit obtaining for a signal at 10MHZ smaller ripple (<1%), faster settling (0.4mus) and using smaller silicon area

A Novel CMOS Envelope Detector Structure

A novel high performance envelope detector is offered in this work. Proposed circuit holds the signal peaks in two periods and combines them to obtain the envelope of the signal. This way, ripple is fixed by the peak holder and tracking can be improved without the traditional compensation between keeping and tracking required in these circuits. A comparison is offered between a conventional circuit, a previous work and the proposed envelope detector. It is shown the superior performance of the latter obtaining small ripple (<1%), fast settling (0.4mus) and high linearity.

Fast-Settling Envelope Detectors

An approach to the design of two high performance envelope detectors is made in this work. Proposed structures do not need the traditional compensation between keeping and tracking required in these circuits. The procedure relies on using a couple of sample-and-hold detectors and combines them to obtain the envelope of the signal. Simulation results are offered and it is shown the superior performance of the proposed detectors comparing with the conventional ones

3.125 Gb/s temperature compensated CMOS optical preamplifier with automatic gain control

This paper presents a low-voltage variable preamplifier with automatic gain control, which works at 3.125 Gb/s in the optical standard 10Gbase-LX4. The system incorporates a circuit that minimizes the temperature effects. The preamplifier achieves adaptive transresistance, 60-74 dBOmega, with an almost constant bandwidth, 2.2 GHz, and with no peaks in the frequency response. The circuit was designed in 0.18 mum CMOS technology with a single 1.8 V supply voltage.