M.T. Sanz

Low-Voltage Linearly Tunable CMOS Transconductor With Common-Mode Feedforward

This paper presents a new low-voltage pseudodifferential continuous-time CMOS transconductor for wide-band applications. The proposed cell is based on a feedforward cancellation of the input common-mode signal and keeps the input common mode voltage constant, while the transconductance is easily tunable through a continuous bias voltage. Linearity is preserved during the tuning process for a moderate range of transconductance values. Measurements results for a 0.35-m CMOS design show a 1:2 tuning range with total harmonic distortion figures at 10 MHz below 58 dB over the whole range up to a 200- differential output current. The proposed cell consumes less than 1.1 mW from a single 1.8-V supply.

Designing Adaptive Conditioning Electronics for Smart Sensing

This paper presents a robust digitally programmable CMOS analogue processor designed for sensor output conditioning in embedded applications. In addition, system adaptability allows for correction of the deviations in circuit operation due to ageing, mismatch or environmental effects, lending a smart nature to the devices. In order to tune the free parameters of the system, two training strategies based on perturbative algorithms are compared. The processor performance is validated by adjusting the response of an angular position sensor and the insensitivity to parameter mismatch is demonstrated through high-level simulations based on Monte Carlo electrical simulation data.

A low-power high-sensitivity CMOS voltage-to-frequency converter

This paper presents a low-cost high-speed CMOS voltage-to-frequency converter (VFC) which targets front-end sensor interfacing in wireless sensor networks applications. The proposed VFC, designed in a 0.35 µm CMOS technology supplied at 3 V, is very simple, obtaining at the same time high performance characteristics: it operates with a power consumption below 1.03 mW at output frequencies ranging from 1.198 MHz to 2.186 MHz given a 1.0–2.0 V input (1 MHz/V sensitivity) with an accuracy better than 1 %.

1.8 V-100 MHz CMOS programmable gain amplifier

This paper presents a low-voltage low-power differential programmable gain amplifier (PGA) for wideband applications. The proposed cell is based on a gm-boosted source degenerated differential pair with a hybrid polysilicon-MOS resistor degeneration structure. Fabricated in a 0.35 mum CMOS technology, the PGA consumes less than 0.5 mW at a single 1.8 V supply. Measured results for a 3-bit implementation show a 0 to 18 dB linear-in-dB programmable gain with a constant bandwidth of 100 MHz when driving 150 fF capacitive loads. Distortion levels are below -72 dB over the whole gain range at 10 MHz for a 0.2 Vp-p differential output

High-Speed High-Precision CMOS Current Conveyor

In this paper a new class-AB CMOS second generation current conveyor (CCII) based on a novel high-performance voltage follower topology is proposed. Post-layout simulation results from a 0.8 μm design supplied at 3.3 V show very low resistance at node X (< 50 Ω), high frequency operation (∼100 MHz), high precision in the voltage and current transference and reduced offset. As application examples, a V-I converter and a current feedback operational amplifier (CFOA) have been implemented. The latter presents slew-rate levels higher than ±100 V/μs.

Precision CMOS current reference with process and temperature compensation

This paper presents a new first-order temperature compensated CMOS current reference. To achieve a compact architecture able to operate under low voltage with low power consumption, it is based on a self-biasing beta multiplier current generator. Compensation against temperature is achieved by using instead of an ordinary resistor two triode transistors in parallel, acting as a negative and a positive temperature coefficient resistor, that generate a proportional to absolute temperature and a complementary to absolute temperature current which can be directly added to attain a temperature compensated current. Programmability is included to adjust the temperature coefficient and the reference current magnitude over process variations. Results for a 0.18 μm CMOS implementation show that the proposed 500 nA reference operate with supplies down to 1.2 V accomplishing over a (-40 to +120°C) range temperature drifts below 120 ppm/°C.

Low-voltage Low-power CMOS Programmable Gain Amplifier

This paper presents a low-voltage low-power intermediate frequency (IF) programmable gain amplifier (PGA). To achieve low-voltage low-power and wideband operation while preserving linearity, the proposed cell is based on a very simple gm-boosted differential pair degenerated with a hybrid polysilicon-MOS programmable resistor structure. Fabricated in a 0.35 mum CMOS technology, the PGA consumes less than 0.5 mW at a single 1.8 V supply. Results for a 3-bit implementation show a 0 to 18 dB linear-in-dB programmable gain with a constant bandwidth of 100 MHz when driving 150 fF capacitive loads. Distortion levels are below -72 dB over the whole gain range at 10 MHz for a 0.2 Vp-p differential output. It shows, compared with other previously reported designs, a good trade-off when all PGA parameters are considered

CMOS digitally programmable cell for high frequency amplification and filtering

This paper presents an approach to the implementation of systems combining variable gain amplifiers (VGA) and programmable continuous-time G/sub m/-C filters in the video frequency range. The technique relies on the use of a versatile high-performance transconductance amplifier as an active cell. Simulation results from 35 /spl mu/m designs supplied at 3.3 V show a 0 to 16 dB gain setting range for the VGA, while G/sub m/-C integrators present a wide tuning range (10 to 100 MHz), with no degradation of the dynamic range (better than 60 dB) and low excess phase (<0.5/spl deg/) over the whole tuning range.

El soporte de autonomía en Educación Física como medio de prevención de la oposición desafiante del alumnado. [Autonomy support in Physical Education as a means of preventing students’ oppositional defiance].

Resumen es: El sistema de clasificacion del slalom en silla de ruedas contempla como elegibles a deportistas con paralisis cerebral y dano cerebral adquirido. La ten...

Low-Voltage Linearly Tunable CMOS Transconductor with Common-Mode Feedforward

This paper presents a new low-voltage pseudo-differential continuous-time CMOS transconductor for wideband applications. The proposed cell is based on a feedforward cancellation of the input common-mode signal and keeps the input common mode voltage constant, while the transconductance is easily tunable through a continuous bias voltage. Linearity is preserved during the tuning process for a moderate range of transconductance values. Simulation results for a 0.35 mum CMOS design show a 1:2 Gm tuning range with an almost constant bandwidth over 600 MHz. Total harmonic distortion figures are below -60 dB over the whole range at 10 MHz up to a 200 muAp-p differential output. The proposed cell consumes less than 1.2 mW from a single 2.0 V supply