J.M. Roux

Hot-Carrier acceleration factors for low power management in DC-AC stressed 40nm NMOS node at high temperature

Channel Hot-Carrier degradation presents a renewed interest in the last NMOS nodes where the device reliability of bulk silicon (core) 40nm and Input/Output (IO) device is difficult to achieve at high temperature as a function of supply voltage VDD and back bias V<inf>BS</inf>. A three mode interface trap generation is proposed based on the energy acquisition involved in distinct interactions in all the V<inf>GS</inf>, V<inf>DS</inf> (V<inf>BS</inf>) conditions as a single I<inf>DS</inf> lifetime dependence is observed with V<inf>GD</inf> > 0. This gives a new age(t) function useful for accurate DC to AC transfers. Positive temperature activation is explained by the rise of ionization rate with electron-electron scattering (medium I<inf>DS</inf>) and multi vibrational excitation (higher I<inf>DS</inf>) which increase the H desorption by thermal emission. The use of forward VBS has shown no gain under CHC for both device types. The main limitation occurs under reverse V<inf>BS</inf> = −V<inf>DD</inf> in IO where the smaller temperature activation partially compensates the larger damage. In that case a security margin can be established giving a limit of V<inf>BS</inf> = −V<inf>DD</inf>/2 for design reliability.

Combined effect of NBTI and channel hot carrier effects in pMOSFETs

This work shows that the channel hot carrier (CHC) degradation for a p-MOSFET consists of two different regimes. At low V/sub g/, the degradation is dominated by hot electrons produced by impact ionization. The hot electrons are responsible for the creation of both interface traps and electron traps within the oxide. At high V/sub g/, a NBT-induced hot carrier effect is evidenced as well as an anomalous CHC effect. This work should help understanding the CHC degradation of pMOSFET as well as determining the worst case degradation.

Novel hot-carrier AC-DC design guidelines for advanced CMOS nodes

The understanding of the relationship between circuit lifetime and device DC hot carrier (HC) stress lifetime is becoming increasingly important for advanced nodes since supply voltage (Vdd) and channel length (L) do not scale anymore in similar proportions. This paper proposes a novel approach to tackle HC risk assessment through a combination of refined transistor HC modeling, Wafer Level Reliability (WLR) & High Temperature Operating Lifetest (HTOL) experimental results and simulations.

Post breakdown oxide lifetime based on digital circuit failure

The Reliability margin of aggressively scaled SiO-based gate dielectrics is strongly reduced. However, the first breakdown (BD) event of ultrathin oxide MOS devices does not always cause the functional failure of digital circuits. This opens the possibility of gaining additional reliability margins from the post-BD stage and has motivated a lot of research in this field. One of the areas of activity has been the study of the statistics of successive BD events because a very important chip lifetime enhancement is obtained when a number of BD events are tolerated without chip failure. However the lifetime extension based on basic transistor parameters shift DeltaVt, DeltaIdsat after breakdown is lacking. This paper provides the first methodology which extends the lifetime of a broken transistor using typical transistor failure criteria: DeltaVt = 50 mV and DeltaIdsat = 10%. The lifetime extension provided by this new methodology is compared to lifetime extension based on multiple breakdowns on a same device and on the chip.

Correction of Self-Heating for HCI Lifetime Prediction

Self-heating (SH) effects, observed during the development of SOI technology for high performance circuits, raise questions concerning the validity of the extrapolation method used for hot carrier injection (HCI). The integration of buried oxide, with low thermal conductivity, enhances self-heating (SH) in MOS transistor devices submitted to DC HCI stress, and leads to potential erroneous HCI lifetime prediction. In this paper, the authors propose a new methodology for the lifetime prediction based on DC HCI stress for SOI technology. The SH is quantified using coupled DC HCI stress and gate resistance measurements, for different transistor widths (W). Then, the degradation part due to SH is removed enabling accurate HCI lifetime prediction.

Reliability issues for nano-scale CMOS dielectrics: - From transistors to product reliability - - From SiON to high-k dielectrics -

Continuous scaling, necessary for enhanced performance and cost reduction, has pushed existing CMOS materials much closer to their intrinsic reliability limits, forcing reliability engineers to get a better understanding of circuit failure. This requires that designers will have to be very careful with phenomena such as high current densities or voltage overshoots. In addition to the reliability issues, new materials as metal gates and high-k gate dielectrics have been integrated. These new materials require that we gain understanding of the reliability physics related to these new materials and that we develop high confidence-level design rules. These new materials require a high understanding level of their reliability issues, as well as the development of high confidence level design rules.

Effect of Self-Heating on HCI Lifetime Prediction in SOI Technologies

In this work we have characterized the self-heating in NMOS transistors using gate resistance methodology. The resulting self-heating model was used to estimate the channel temperature during DC HCI stress. Furthermore, the same model (Arrhenius) was used to extrapolate HCI lifetime corresponding to analog and digital applications. And this is demonstrated for NMOS transistor and for PMOS transistor. This is the first investigation of SH impact on HCI DC degradation for both analog and digital applications and the first proposed methodology to correct HCI DC dataset from SH contribution

CMP-less integration of 40nm-gate totally silicided (TOSI) bulk transistors using selective S/D Si epitaxy and ultra-low gates

In this paper, we present an innovative way of fabricating CMOS transistors with totally Ni-silicided (Ni-TOSI) gates without using a CMP step before the full gate silicidation. The combination of the use of a hard-mask-capped ultra-low Si gate with a selective S/D epitaxy step enables us to obtain a well-behaved silicidation of the junctions and the full gate within one single step with minimal gate lengths of 40nm. Moreover, we show that the TOSI PMOS device performances are compatible with the 45nm-node LP requirements. Reliability data is added demonstrating that no additional breakdown mechanisms occur after the TOSI process.

New insight into the relation between Hot Carrier degradation and oxide breakdown through MVHR

Most of the oxide breakdown studies are based on the results of measurements in which the oxide is uniformly stressed thus avoiding the HCI (hot carrier injection) regime. As devices typically undergo hot carrier degradation during their operation, ignoring HCI degradation may result in overestimation of the oxide lifetime. In this paper, a deeper understanding of the relation between HCI and oxide breakdown is obtained based on MVHR (multivibrational hydrogen rRelease) mechanism. Subsequently we model the time to breakdown at different Vg, Vd conditions enabling oxide lifetime assessment in such stress conditions.

Ageing under illumination of MOS transistors for active pixel sensors (APS) applications

This paper presents new reliability investigations on CMOS transistors for active pixels sensors (APS) applications. Reliability tests under sunlight illumination show an ageing effect of the transistors. The dependence of the degradation with light intensity and stress bias has been studied. The use of borderless silicon nitride is suspected to be responsible of this degradation: charges in this nitride can move under illumination and modulate the conductivity of a special implantation region of the transistor.