M. Rafik

High-K gate stack breakdown statistics modeled by correlated interfacial layer and high-k breakdown path

We show that a model in which the breakdown of the interfacial layer induces a correlated breakdown in the high-K, at the same location, provides a good model of the high-K/IL gate stack statistics. We discuss of the implication of this model on the lifetime projection.

28nm node bulk vs FDSOI reliability comparison

In this paper, we present TDDB, HCI and BTI reliability characterization of Nfet and Pfet devices issued from FDSOI and bulk 28nm technologies. 28nm FDSOI devices achieve 32% improved performance, 40% reduced power consumption and improved matching. From device level tests, 28nm FDSOI also demonstrates intrinsic reliability behavior similar to 28 bulk devices, giving confidence in the robustness of this technology.

Hot carrier degradation: From defect creation modeling to their impact on NMOS parameters

Hot Carrier induced degradation is modeled using the carrier energy distribution function including Carrier-Carrier Scattering process. Silicon-hydrogen bond breakage through single particle and multiple particles interactions is considered in the modeling of the microscopic defect creation along the channel. Good agreement with lateral profile measurements is obtained for various stress conditions. The impact of the simulated defects distribution along the channel on the electrostatic and mobility (using remote coulomb scattering) is found in line with measurements.

PBTI mechanisms in La containing Hf-based oxides assessed by very Fast IV measurements

PBTI in La-doped HfSiON/TiN stacks is investigated using Ultra Fast IV measurements. Excellent PBTI lifetime of these oxides is demonstrated. We also show that PBTI is explained only by trapping in stress induced defects and not by trapping in pre-existing ones. Dependence on oxide field, temperature activation and recovery of PBTI are also investigated and modeled.

New Understanding on the Breakdown of High-K Dielectric Stacks using Multi-Vibrational Hydrogen Release Model

The breakdown of HfO2, HfZrO2 and HfSiON gate stacks with TiN metal gate under substrate injection regime is investigated and confronted with the multivibrational hydrogen release model. It turns out that for HfO2 and HfZrO2 because no Si-H bonds are present at the TiN interface, MVHR from Si-H bonds can not take place. Moreover, even adapting the model by supposing hydrogen release from another type of bond, or considering other conventional models, breakdown mechanism remains undefined. Nevertheless, for HfSiON for which Si-H bonds are present, modeling based on MVHR becomes consistent with experimental values.

Interaction between BTI and HCI degradation in High-K devices

In this paper we review experiments combining several types of FET devices degradation modes, including HCI, bias and unbiased BTI. We analyze the nature and localization of defect issued from these degradation processes and derive rules governing interaction between defect generation process, drain polarization dependency on BTI degradation as well as potential BTI contribution to HCI degradation. Consequences of BTI - HCI interaction on WLR analysis as well as product operation will be discussed.

Process dependence of BTI reliability in advanced HK MG stacks.

Bias temperature instabilities (BTI) reliability is investigated in advanced dielectric stacks. We show that mobility performance and NBTI reliability are strongly correlated and that they are affected by the diffusion of nitrogen species N at the Si interface. PBTI, more sensitive to bulk oxide traps, is strongly reduced in very thin dielectric films. Reducing the metal gate thickness favors the reduction of mobility degradations and NBTI, but, also strongly enhances PBTI, due to a complex set of reactions in the gate oxide. Trade off must be found to obtain a great trade off between device performance and reliability requirements.

Post breakdown oxide lifetime based on digital circuit failure

The Reliability margin of aggressively scaled SiO-based gate dielectrics is strongly reduced. However, the first breakdown (BD) event of ultrathin oxide MOS devices does not always cause the functional failure of digital circuits. This opens the possibility of gaining additional reliability margins from the post-BD stage and has motivated a lot of research in this field. One of the areas of activity has been the study of the statistics of successive BD events because a very important chip lifetime enhancement is obtained when a number of BD events are tolerated without chip failure. However the lifetime extension based on basic transistor parameters shift DeltaVt, DeltaIdsat after breakdown is lacking. This paper provides the first methodology which extends the lifetime of a broken transistor using typical transistor failure criteria: DeltaVt = 50 mV and DeltaIdsat = 10%. The lifetime extension provided by this new methodology is compared to lifetime extension based on multiple breakdowns on a same device and on the chip.

Experimental analysis of defect nature and localization under hot-carrier and bias temperature damage in advanced CMOS nodes

We present a multi techno trend of HCI time acceleration and VD power law exponent for various processes. We review the results of defect localization analysis based on a rigorous correlation and interaction study for different HCI degradation modes and BTI. Finally, we check HCI impact on TDDB to get an accurate comprehension about defect nature. Hence, we point out the necessity of new appropriate reliability modeling specially for recent ultra-short channel technologies.

Impact of backside interface on Hot Carriers degradation of thin film FDSOI Nmosfets

Based on simulation results, we show that defects at the Si/Box interface of FDSOI transistors can have a detrimental impact on reliability. In particular, attention is paid to Hot Carriers degradations (HC) on ultra thin film FDSOI NMOSFETs for which defects can be created very close to the back gate interface. A new technique based on capacitance measurements is proposed to localize HC degradation at front gate and/or back gate interface on FDSOI transistors. Thanks to this method, it is shown that, similarly to bulk technologies, only the front gate interface is degraded during a classical HC stress. Finally, despite the presence of an additional Si/BOx interface, FDSOI NMOSFETs down to 30nm gate length exhibit HC lifetimes over 10 years, even when a back bias is applied.