J. Neil Merrett

Design and fabrication of planar guard ring termination for high-voltage SiC diodes

Abstract An optimized multiple floating guard ring structure is investigated for the first time as an edge termination method for high voltage 4H-SiC planar devices. Simulations were performed to investigate SiC guard ring termination, and determine the optimum guard ring spacing for planar diodes with up to four floating rings. Simulated optimized designs predicted breakdown values from 40% of the ideal breakdown with a single ring, to 84% of the ideal value for diodes with four rings. Implanted 4H-SiC pn diodes with optimized guard ring designs were fabricated and results correlated to simulation. Experimental breakdown values of 1.2–1.3 kV for guard ring structure with four rings were in good agreement with simulated results.

Gamma and Proton Irradiation Effects on 4H-SiC Depletion-Mode Trench JFETs

4H-SiC vertical depletion-mode trench JFETs were fabricated, packaged, and then irradiated with either 6.8 Mrad gamma from a 60Co source, a 9x1011 cm-2 dose of 4 MeV protons, or a 5x1013 cm-2 dose of 63 MeV protons. 4H-SiC Schottky diodes were also fabricated, packaged and exposed to the same irradiations. The trench VJFETs have a nominal blocking voltage of 600 V and a forward current rating of 2 A prior to irradiation. On-state and blocking I-V characteristics were measured after irradiation and compared to the pre-irradiation performance. Devices irradiated with 4 MeV proton and gamma radiation showed a slight increase in on resistance and a decrease in leakage current in blocking mode. Devices irradiated with 63 MeV protons, however, showed a dramatic decrease in forward current. DLTS measurements were performed, and the results of these measurements will be discussed as well.

Fast Switching (41 MHz), 2.5 mΩ•cm2, High Current 4H-SiC VJFETs for High Power and High Temperature Applications

In this work we have demonstrated the operation of 600-V class 4H-SiC vertical-channel junction field-effect transistors (VJFETs) with 6.6-ns rise time, 7.6-ns fall time, 4.8-ns turn-on and 5.4-ns turn-off delay time at 2.5 A drain current (IDS), which corresponds to a maximum switching frequency of 41 MHz – the fastest ever reported switching of SiC JFETs to our knowledge. At IDS of 12 A, a 19.1 MHz maximum switching frequency has been also achieved. Specific on-resistance (Rsp-on) in the linear region is 2.5 m·cm2 at VGS of 3 V. The drain current density is greater than 1410 A/cm2 at 9 V drain voltage. High-temperature operation of the 4H-SiC VJFETs has also been investigated at temperatures from 25 °C to 225 °C. Changes in the on-resistance with temperature are in the range of 0.90~1.33%/°C at zero gate bias and IDS of 50 mA. The threshold voltage becomes more negative with a negative shift of 0.096~0.105%/°C with increasing temperature.

A Review of SiC Power Switch: Achievements, Difficulties and Perspectives

The need to minimize losses in power electronic systems has led to the recent boost in silicon carbide (SiC) power technology. Superior properties of SiC such as high critical electric field, high saturation drift velocity, and high thermal conductivity make this material ideally suited for high voltage high power applications. The voltage spectrum of the potential applications where SiC power rectifiers and switches are expected to replace their silicon counterparts ranges from tens of volts for display drives to tens of kilovolts for traction applications and high voltage dc transmission (HVDC) systems. Despite the fundamental material advantages of SiC over the other well-established semiconductor materials such as Si and GaAs, new designs and fabrication techniques are still to be developed to fully realize the inherent potential of SiC devices in highpower switching applications. In this work, a detailed review of the current situation and future trends in SiC power switching device technology is given with an emphasis on design and processing issues. This paper discusses the recent development of power SiC switches and identifies the key issues in processing and device structures which have influenced past and will impact future SiC product development.

Fabrication and Simulation of 4H-SiC PiN Diodes Having Mesa Guard Ring Edge Termination

We report on the design, simulation and fabrication process of 4H-SiC PiN diodes using p-type mesa guard ring (MGR) edge termination. The fabri cated diodes had 10m ntype drift regions with doping of ~2x10 16 cm, and MGRs formed in 0.5 μm p+ layer with active acceptor concentration of approximately 4x10 18 cm. The diodes have probed forward current density of 1 kA/cm at 7.5 V forward drop and average 850 V breakdown voltages, while the best devices demonstrated 1100 V breakdowns. Both the device a ctive areas and guard rings were defined during the same fabrication step using a SF6 ICP etch. MGRs with a width and spacing of 2 μm were fabricated with a varying number o f rings ranging from 4 to 20. Introduction In recent years, the best reported high voltage SiC PiN diodes we re fabricated using JTE Junction Termination Extension (see for example, [1]). Despite the e xc ll nt electrical performance, this technique has several drawbacks which limit its pr actical implementation. First, JTE requires an additional implantation, and sometimes an addi tional post-implant annealing step. Second, to be most effective, JTE’s active concentra tion h s to be precisely tailored to fit the doping profile in the device drift region. Even small variation in the epi doping and the activation percentage of the acceptors in JTE region may cause significant changes in the device blocking voltage. In addition, fast high-voltage pulses may cause breakdown voltage instabilities due to incomplete post-implant activat ion nd carrier freezeout issues, typical for p-type impurities in SiC [2]. In this w ork we suggest the application of mesa guard rings (MGRs) as a promising edge termination tec h ique for SiC PiN diodes [3]. In comparison with traditional implanted guard rings, MGRs offer a potential for low-cost, lowdamage edge termination because expensive ion-implantation and post-implant anneal steps are unnecessary. In the following sections we discuss the device structure, simulation, fabrication process and experimental results of the PiN diodes having p-type mesa guard rings edge termination compared to traditional ionimplanted guard rings and JTE techniques. a) b) Figure 1: SEM picture of device structure after SF 6 ICP etch: top view of a 4-ring, 0.01 mm 2 device (a), and MGRs at 15 K magnification (b) Materials Science Forum Online: 2003-09-15 ISSN: 1662-9752, Vols. 433-436, pp 879-882 doi:10.4028/www.scientific.net/MSF.433-436.879

RF and DC Characterization of Self-Aligned L-Band 4H-SiC Static Induction Transistors

Trenched, vertical SiC static induction transistors (SIT) for L-band power amplification were fabricated with implanted p-n junction gates on conducting n-type 4H-SiC substrates using a self-aligned fabrication process. The self-aligned fabrication process required no critical alignments and allowed for high channel packing densities ranging from 2.9x103 to 5x103 cm/cm2. Devices were fabricated with a range of finger widths. Devices with the narrowest fingers were able to block up to 450 V with VGS = -3 V. Devices with wider fingers required higher gate voltages ranging from -10 V to -25 V to achieve similar blocking. Devices were packaged and small-signal and loadpull measurements were taken with the devices externally matched. Devices having the narrowest finger design had a small-signal power gain of over 9 dB at around 1.3 GHz. Load-pull measurements of packaged SITs with 1 cm gate periphery yielded a maximum power gain of ~ 8.2 dB at 1 GHz, VDD = 100 V, and VGS = 1.2 V. Due to the high packing density, these results translate to power densities of 22 kW/cm2.

Design and Implementation of the Optimized Edge Termination in 1.8 kV 4H-SiC PiN Diodes

One of the key issues limiting the commercialization of power SiC rectifiers and switches is the poor yield due to the absence of an effective and reliable edge termination. Efficient edge termination allows for a thinner and heavier doped voltage blocking layer, which directly reduces conduction losses. The focus of this work was to optimize the efficiency and reproducibility of the edge termination technique. For that purpose, 4H-SiC PiN diodes were fabricated with Junction Termination Extension (JTE) created by B + and Al + implantation. The JTE-terminated 4H-SiC PiN diodes fabricated in this work exhibited stable reverse bias operation with avalanche breakdown occurring at 1.8 kV. This voltage corresponds to the maximum one-dimensional electric field of 2.67 MV/cm in the blocking layer under the pn junction. Forward voltage drops of 5 V and 8 V were associated with current densities of 1.2 kA/cm 2 and 6.5 kA/cm 2 respectively. Measurement results obtained on the fabricated devices closely matched the simulation results, which confirms the reproducibility and scalability of the design to much higher blocking voltage and forward current levels.