Mohamed Azimane
Philips
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Publication
Featured researches published by Mohamed Azimane.
vlsi test symposium | 2004
Mohamed Azimane; Ananta K. Majhi
Intra-gate resistive open defects not only cause sequential behaviour in CMOS memory address decoders, but also lead to delay behaviour. This paper evaluates the fault coverage of the resistive open defects in the memory address decoders. It shows that both the strong and the weak open defects are not completely covered by applying the well-known March tests and special test pattern sequences published in the literature. We demonstrate that the fault coverage is increased by varying the duty cycle of the internal clock of the address decoder. For the self-timed memories, we introduce a simple DFT technique to control the duty cycle of the internal clock which activates/deactivates the word lines. Using defect-oriented test, we also created a fault dictionary based on the defect location, transistor types, the terminal name and also the faulty behaviour. The fault dictionary in combination with the bit-map fail data will facilitate the localization of the open defects.
design, automation, and test in europe | 2005
Ananta K. Majhi; Mohamed Azimane; Guido Gronthoud; Maurice Lousberg; Stefan Eichenberger; Fred Bowen
This paper presents the effectiveness of various stress conditions (mainly voltage and frequency) on detecting the resistive shorts and open defects in deep sub-micron embedded memories in an industrial environment. Simulation studies on very-low voltage, high voltage and at-speed testing show the need of the stress conditions for high quality products; i.e., low defect-per-million (DPM) level, which is driving the semiconductor market today. The above test conditions have been validated to screen out bad devices on real silicon (a test-chip) built on CMOS 0.18 /spl mu/m technology. The IFA (inductive fault analysis) based simulation technique leads to an efficient fault coverage and DPM estimator, which helps the customers upfront to make decisions on test algorithm implementations under different stress conditions in order to reduce the number of test escapes.
vlsi test symposium | 2005
Mohamed Azimane; Ananta K. Majhi; Guido Gronthoud; Maurice Lousberg; Stefan Eichenberger; A.L. Ruiz
Resistive bridges not only cause a static faulty behavior in CMOS memories, but also lead to several dynamic faulty behaviors which are timing related failures. This paper introduces a new realistic dynamic fault model for random access-memories: the delay coupling fault, which models resistive bridges in the memory array. We show that well-known march tests do not cover delay coupling faults at the memory array. To cover the delay coupling faults, a new and efficient test algorithm (DITEC+) is presented. We have performed inductive fault analysis to validate this novel algorithm and shown a significant improvement on fault coverage. Also, experiment on silicon is carried out to show the existence of such dynamic faults and their detection by implementing DITEC+.
european solid-state circuits conference | 2005
Ananta K. Majhi; Mohamed Azimane; Guido Gronthoud; Maurice Lousberg; Stefan Eichenberger; F. Bowen
This paper presents the effectiveness of various stress conditions (mainly voltage and frequency) on detecting the resistive shorts and open defects in deep sub-micron embedded memories in an industrial environment. Simulation studies on very-low voltage, high voltage and at-speed testing show the need of the stress conditions for high quality products. The above test conditions have been validated to screen out the bad chips on real silicon (on a test-chip) built on CMOS 0.18 /spl mu/m technology.
memory technology, design and testing | 2006
Mohamed Azimane
Semiconductor Companies are continuously trying to keep their customers Happy and Satisfied with new products, new functionalities and new interfaces. To keep track on inventing products with new more facilities, Semiconductor Companies have to include much more transistors per millimeter square than ever before. Nowadays, System on Chips (SoCs) are very dense, approaching 1 billion of transistors per chip of few millimeters. Interaction of this huge number of transistors in a chip is becoming much more important than few years ago. To be specific, in current process technologies new defects mechanisms and process variation are causing complex faulty behaviours, which are creating new challenges for test experts. Moreover, embedded memories occupy a big portion of SoCs approaching nowadays 70% of total SoC area and are infringing the DFM rules, which creates even higher defect density than logic or analog blocks. This tutorial will give an overview about high quality memory testing in industrial environment, and how Semiconductor Companies are surviving in competitive markets by delivering high quality products and targeting for Zero Defect escapes for specific customers (e.g., Automotive, Medical Systems, Avionics, etc.). Also, an overview about closing the loop with memory designers and process engineers in early phase of the design is highlighted. Such loop could easily improve the test & yield of embedded memories in short market time window by taking decisive actions on layout level.
Archive | 2005
Jose de Jesus Pineda De Gyvez; Mohamed Azimane; Andrei Pavlov
Archive | 2005
Mohamed Azimane
Archive | 2004
Mohamed Azimane; Ananta K. Majhi
Archive | 2005
Mohamed Azimane; Ananta K. Majhi
Archive | 2005
Mohamed Azimane; Ananta K. Majhi