J. Tom M. Stevenson

Cost-effective overlay and CD metrology on phase-shifting masks

This paper presents the use of specially designed electrically testable structures to measure characteristics of alternating aperture phase-shifting masks (altPSM). The linewidths of chrome features on the mask are measured using modified cross-bridge structures, the technique behind this is explained together with the specific designs used to characterise both dense and isolated features. A practical, manufacturable solution to overcoming the problem of the non-conductive anti-reflective chromium oxy-nitride is given and results shown to prove its success. Correlation to more conventional CD measurements reinforce this result. A new technique, to measure the overlay of the second laye, used in the mask manufacture as the mask for the quartz etch establishing the phase shifted areas, is discussed. This entails using capacitive test structures in a progressional offset array to establish the minimum capacitance, indicating the overlay achieved. This technique has the added advantage of removing the errors created by mask sag in overlay metrology tools where the mask is held only at the edge. Results are presented indicating the success of this technique.

Electrical test structures for the characterisation of optical proximity correction

Simple electrical test structures have been designed that will allow the characterisation of corner serif forms of optical proximity correction. The structures measure the resistance of a short length of conducting track with a right angled corner. Varying amounts of OPC can be applied to the outer and inner corners of the feature and the effect on the resistance of the track measured. These structures have been simulated and the results are presented in this paper. In addition a preliminary test mask has been fabricated which has test structures suitable for on-mask electrical measurement. Measurement results from these structures are also presented. Furthermore structures have been characterised using an optical microscope, a dedicated optical mask metrology system, an AFM scanner and finally a FIB system. In the future the test mask will be used to print the structures using a step and scan lithography tool so that they can be measured on-wafer. Correlation of the mask and wafer results will provide a great deal of information about the e ects of OPC at the CAD level and the impact on the final printed features.

Realization of a large-area microbolometer sensor array for submillimeter astronomy applications: SCUBA-2

The realization of a large (40x32) pixel sub-array on a 3-inch silicon wafer brings unique challenges involving the integration of a variety of microfabrication techniques. Design, development and fabrication procedures are described, with conventional MEMS techniques in silicon being used where possible. High resolution imaging in the sub-millimetre range requires a pixel size of the order of one millimetre with a high signal/noise ratio detector, which must be addressed at cryogenic temperatures via a very low noise amplifying system. This has been realized using a combination of Transition Edge Sensors (TES) with amplification and multiplexing (MUX) by Superconducting Quantum Interference Devices (SQUID), which imposes particular requirements in the method of construction. This paper describes the details of the technologies used to overcome the conflicting demands of the different elements. The need to operate at millikelvin temperatures limits the materials that can be selected. Particular attention has been paid to the stresses induced in the structure by overlying films, bump bonding and any thermal processing.

Review of the history and technology of micromachined miniature displays using foundry-produced silicon backplanes

Liquid-crystal over silicon is an established technology for reflective spatial light modulators and microdisplays. This paper reviews their development to date, highlighting in particular the micromachining of the mirror array and the associated packaging issues.

Microfabrication and packaging of deformable mirror devices

We describe the fabrication and testing of deformable membrane mirrors over silicon backplanes using our in-house CMOS processing facilities. The fabrication of dense arrays of electrostatic actuators on the backplane potentially allows fine control of the membrane surface shape than can be produced when using a printed circuit board as the backplane. We presents a range of techniques for fabrication the membrane mirrors in various materials and mating the structure to a silicon backplane. We characterise membrane deflection with electric field for silicon nitride and polymer membranes over a passive silicon backplane consisting of 37 directly-addressed electrode pads configured in a hexagonal array.

Post-processing using microfabrication techniques to improve the optical performance of liquid crystal over silicon backplane spatial light modulators

Liquid crystal (LC) over silicon backplane spatial light modulators (SLMs) have applications in optical processing and as miniature displays. With these devices a LC layer is sandwiched between the silicon backplane and a front cover glass coated with a transparent ITO electrode. The voltage between electrodes on the controlling circuitry and the ITO electrode determines the state of the LC which in turn is used to modulate incident light onto the device. The silicon backplane consists of an array of pixels similar to DRAM or SRAM devices but where each pixel controls the voltage on an electrode. These electrodes must also act as mirrors reflecting the incident light. The silicon backplanes supplied by commercial foundries which work well electrically suffer from having poor optical quality pixel mirrors. These mirrors have inferior surface quality with low flat fill factor resulting in low optical efficiency. Hillocks are also present which cause problems with LC cell construction. We have developed a post-processing procedure based on silicon microfabrication techniques to add another level of metal to commercially fabricated wafers which addresses these problems. To ensure that his new metal layer is deposited onto a very flat substrate the interlevel dielectric is planarized using chemical mechanical polishing. We have developed this technique to produce an optical quality surface with local surface variations of less than 100 angstrom consistently achieved. The deposited aluminium top layer is optimized for best optical performance within the constraints of the electrical characteristics. Pixel mirrors with flat fill factors up to 84% were realized which improved the optical efficiency of the SLM. No hillocks were present on the metal surface presenting the opportunity to fabricate 1 micrometers thick LC cells to fully utilize the potential of ferroelectric LC. We will also report on a n expansion of the post-processing procedure to protect devices based on DRAM memory layout from photo induced charge leakage. The use of microfabrication techniques to construct the LC spacer layer will also be discussed.

64x64 smart pixel array for deformable membrane devices

In this paper we describe the development of a CMOS VLSI backplane for use with micromachined silicon nitride membrane mirrors. The backplane consists of an array of 4096 pixels which are addressed by a 6-bit row decoder. Data enters the chip as a 64-bit logic word at standard CMOS 0-5V levels and is converted to 0-50V at the pixel level by an optimized cascade voltage switch logic circuit.

Fabrication of spatial light modulator backplanes using damascene processing

The alignment of ferroelectric liquid crystal (FLC) is heavily influenced by the FLC flow rate during SLM cell filling. This flow rate is affected by a number of factors, one aspect of which is the structure of the silicon backplane. Even when the device has been planarized the structure of the pixelated top layer metal still influences the FLC flow rate and therefore the FLC alignment. We have produced a flat silicon backplane substrate using damascene processing to manufacture the mirror/electrodes. Damascene processing is a metal polishing technique. In this process the oxide layer which has already been polished is etched to create trenches in the desired pattern of the metal layer, a blanket deposition of metal is then performed, which fills the trenches and covers the wafer surface, finally CMP is performed, which removes the excess material on the wafer surface leaving the metal in the trenches and the top surface flat. There are some problems associated with damascene processing which will affect its suitability in the micro-=fabrication of SLM backplanes. The softer metal material is prone to dishing and scratching and the harder oxide material can be eroded. THese effects are dependent on the level of control of the CMP process. A process is being developed, using novel slurry chemistries, to allow the incorporation of this technique into our post-processing procedure. The results of the application of this process to test structures and an analysis of the suitability of this technique in the microfabrication of SLM silicon backplanes will be presented.

Photoresist dissolution rates: a comparison of puddle, spray, and immersion processes

Design and operation of an on-line Track Development Rate Monitor (TDRM) for track development systems are described. Dissolution data, measured using this equipment, for spray and puddle development processes is presented and compared to those derived from a conventional immersion DRM. Immersion data has traditionally been used to model all development. The validity of this is discussed. Also presented is an off-line technique for evaluating dissolution rates which utilize no specialized DRM equipment. The dissolution rates as measured by this technique are compared with those obtained from the TDRM/DRM methods. Simulations using all the calculated dissolution parameters are compared with SEM cross sections so that a practical evaluation of the various techniques can be made.

Electrical Test Structures for the Characterisation of Optical Proximity Correction

Simple electrical test structures have been designed that will allow the characterisation of corner serif forms of optical proximity correction. The structures measure the resistance of a short length of conducting track with a right angled corner. Varying amounts of OPC can be applied to the outer and inner corners of the feature and the effect on the resistance of the track measured. These structures have been simulated and the results are presented in this paper. In addition a preliminary test mask has been fabricated which has test structures suitable for on-mask electrical measurement. Measurement results from these structures are also presented. Furthermore structures have been characterised using an optical microscope, a dedicated optical mask metrology system, an AFM scanner and finally a FIB system. In the future the test mask will be used to print the structures using a step and scan lithography tool so that they can be measured on-wafer. Correlation of the mask and wafer results will provide a great deal of information about the e ects of OPC at the CAD level and the impact on the final printed features.