Ian Underwood

Evolutionary development of advanced liquid crystal spatial light modulators

Taking into account recent developments and present trends in devices and component technologies, the future development of electrically addressed liquid crystal spatial light modulators is considered. In particular, the combination of single-crystal-silicon active backplane and chiral smectic C liquid crystal technologies is shown to be promising. The ultimate limitations of such technologies for producing faster devices of higher complexity and functionality are assessed, and an advanced device, presently under development, is described.

A Reconfigurable Single-Photon-Counting Integrating Receiver for Optical Communications

A reconfigurable Single-Photon Avalanche Diode integrating receiver in standard 130 nm CMOS is presented for optical links with an array readout bandwidth of 100 MHz. A maximum count rate of 58 G photon/s is observed, with a dynamic range of ≈ 79 dB, a sensitivity of ≈ - 31.7 dBm at 100 MHz and a BER of ≈ 1 ×10-9. The sensor core draws 89 mW at the maximum count rate and obtains a peak SNR of ≈157 dB. We investigate the properties of the receiver for optical communications in the visible spectrum, using its added functionality and reconfigurability to experimentally explore non-ideal influences. The all-digital 32 × 32 SPAD array, achieves a minimum dead time of 5.9 ns, and a median dark count rate of 2.5 kHz/SPAD. The internal gain of SPADs and spatio-temporal summation removes the need for analogue amplification. High noise devices can be weighted or removed to optimize the SNR. The power requirements, transient response and received data are explored and limiting factors similar to those of photodiode receivers are observed.

Active-Matrix GaN Micro Light-Emitting Diode Display With Unprecedented Brightness

Displays based on microsized gallium nitride light-emitting diodes possess extraordinary brightness. It is demonstrated here both theoretically and experimentally that the layout of the n-contact in these devices is important for the best device performance. We highlight, in particular, the significance of a nonthermal increase of differential resistance upon multipixel operation. These findings underpin the realization of a blue microdisplay with a luminance of 106 cd/m2.

Improving the performance of liquid-crystal-over-silicon spatial light modulators:issues and achievements

The performance of liquid-crystal-over-silicon spatial light modulators has advanced rapidly in recent years. Most progress has centered around new device designs with increased bandwidth. In this paper we report on a number of techniques to improve the optical quality; these have applications in both current and future devices.

Mirror quality and efficiency improvements of reflective spatial light modulators by the use of dielectric coatings and chemical-mechanical polishing

To date, silicon backplane spatial light modulators have been characterized by poor-quality mirrors. Hillock formation during metal sintering has been identified as the source of this problem. Here hillock elimination is achieved by constraining the metal with a low-temperature plasma-enhanced chemicalvapor deposition silicon dioxide coating. A double-layer metallization procedure increases the silicon area available for circuitry and improves the mirror fill factor. Second-layer metal mirrors require a flat, intermediate dielectric substrate. Chemical-mechanical polishing is demonstrated to provide the flatness necessary to achieve high optical quality.

A 256 × 256 SRAM-XOR pixel ferroelectric liquid crystal over silicon spatial light modulator

Abstract An electronically addressed spatial light modulator is introduced. It is based on the hybrid technology of ferroelectric liquid crystal over silicon, and comprises an array of 256 × 256 pixels operating at a charge balanced frame rate of up to 2.1 kHz. The pixel circuit, incorporating a static random access memory latch and an exclusive-OR gate, has significant performance advantages over the single transistor design used elsewhere. The silicon backplane has also been used to help develop post-processing planarisation techniques for high fill-factor (84%), optically flat electrode mirrors.

Optoelectronic systems based on InGaAs–complementary-metal-oxide-semiconductor smart-pixel arrays and free-space optical interconnects

Free-space optical interconnects have been identified as a potentially important technology for future massively parallel-computing systems. The development of optoelectronic smart pixels based on InGaAs/AlGaAs multiple-quantum-well modulators and detectors flip-chip solder-bump bonded onto complementary-metal-oxide-semiconductor (CMOS) circuits and the design and construction of an experimental processor in which the devices are linked by free-space optical interconnects are described. For demonstrating the capabilities of the technology, a parallel data-sorting system has been identified as an effective demonstrator. By use of Batchers bitonic sorting algorithm and exploitation of a perfect-shuffle optical interconnection, the system has the potential to perform a full sort on 1024, 16-bit words in less than 16 mus. We describe the design, testing, and characterization of the smart-pixel devices and free-space optical components. InGaAs-CMOS smart-pixel, chip-to-chip communication has been demonstrated at 50 Mbits/s. It is shown that the initial system specifications can be met by the component technologies.

High-performance spatial light modulator

The development of a ferroelectric liquid-crystal-over-single-crystal-silicon spatial light modulator is described. The reflective SLM has an array of 176 X 176 pixels over a clear aperture of 5.28 mm X 5.28 mm. Prototype devices driven from a specially designed high speed frame store have been operated at frame rates of approximately equals 1 kHz.

Real-time quantitative monitoring of hiPSC-based model of macular degeneration on Electric Cell-substrate Impedance Sensing microelectrodes.

Age-related macular degeneration (AMD) is the leading cause of blindness in the developed world. Humanized disease models are required to develop new therapies for currently incurable forms of AMD. In this work, a tissue-on-a-chip approach was developed through combining human induced pluripotent stem cells, Electric Cell–substrate Impedance Sensing (ECIS) and reproducible electrical wounding assays to model and quantitatively study AMD. Retinal Pigment Epithelium (RPE) cells generated from a patient with an inherited macular degeneration and from an unaffected sibling were used to test the model platform on which a reproducible electrical wounding assay was conducted to model RPE damage. First, a robust and reproducible real-time quantitative monitoring over a 25-day period demonstrated the establishment and maturation of RPE layers on the microelectrode arrays. A spatially controlled RPE layer damage that mimicked cell loss in AMD disease was then initiated. Post recovery, significant differences (P<0.01) in migration rates were found between case (8.6±0.46 μm/h) and control cell lines (10.69±0.21 μm/h). Quantitative data analysis suggested this was achieved due to lower cell–substrate adhesion in the control cell line. The ECIS cell–substrate adhesion parameter (α) was found to be 7.8±0.28 Ω1/2 cm for the case cell line and 6.5±0.15 Ω1/2 cm for the control. These findings were confirmed using cell adhesion biochemical assays. The developed disease model-on-a-chip is a powerful platform for translational studies with considerable potential to investigate novel therapies by enabling real-time, quantitative and reproducible patient-specific RPE cell repair studies.

Techniques to improve the flatness of reflective micro-optical arrays

Abstract Liquid crystal over silicon is an established technology for reflective spatial light modulators and microdisplays. In this paper, we describe progress in improving two key performance criteria. The first is backplane flatness; we describe recent developments in the use of chemical mechanical polishing to produce optically flat pixel mirrors on top of existing circuit topography; we further describe the use of an assembly technique that reduces chip bow caused by the microfabrication induced stresses in the silicon backplane. The second is liquid crystal layer thickness; we describe the use of a lithographically patterned spacer layer microfabricated on the surface of the silicon backplane to minimize layer thickness variations. Each of the techniques produces improvements in the performance of the final device.