R.J. Holwill

A yield improvement technique for IC layout using local design rules

The concept of local design rules is introduced. These are integrated circuit (IC) layout rules that define the optimum feature size and spacing in relation to the surrounding geometry and are used to increase the yield of ICs. The impact of these rules on the performance and reliability of ICs is discussed. Algorithms that enable the automatic application of track displacement, track width, and contact size local design rules to IC layout are presented. Simulation results are provided for some layout examples. >

A novel approach for reducing the area occupied by contact pads on process control chips

An approach which reduces the number of pads required by electrical test structures is presented. The multiplexed scheme requires only two levels of interconnect and enables more devices to be located in a given area, providing the designer of test structures with more freedom to experiment with structures previously requiring a large number of pads. Applications for transistors, electrical verniers, yield monitoring, reliability evaluations, continuity tests, and measuring the resistance of tracks are discussed.<<ETX>>

Numerical simulation of resistive interconnects for integrated circuits

When interconnects for integrated circuits have been modeled, it has been normal to consider them only as straight tracks. In any practical circuit this is not the case and a more rigorous analysis is performed by the authors. The effects of corners and T-junctions are analyzed using finite elements and some models are presented which can be used by circuit designers to simulate circuit performance.

The use of a digital multiplexer to reduce process control chip pad count

A method for more area efficient accessing of digital test structures is reported. It was demonstrated that, for a given number of pads, the diode interconnect scheme, which places a diode in series with each test element to suppress alternate current paths, enables a larger number of test elements to be accessed than would be possible with more conventional methods. Further pad economy was demonstrated by the use of digitally addressed multiplexers which allow on-chip switching of the force and sense instruments to test elements incorporated in the diode interconnect scheme.<<ETX>>

A Novel Approach for an Electrical Vernier to Measure Mask Misalignment

A novel interconnect scheme is presented which reduces the number of pads required by electrical verniers to measure mask misalignment. It makes the use of a shift register no longer necessary to keep the pad count to a reasonable number and the process is only required to support the fabrication of diodes. The vernier can be measured using any test equipment which can test for continuity.

Examination of LOCOS process parameters and the measurement of effective width

Device isolation by means of LOCOS and field implantation are commonly incorporated in current MOS processes. These two process steps interact to affect the effective MOS transistor width. The authors examine the topographical features determined by pad oxide and nitride thicknesses and compare the physical with the effective electrical width. It is concluded that the limit in topographical packing density may be achieved by physical reduction of the birds beak, but for varying pad oxide/nitride mask combinations the effective device width is limited by the presence of the field implant.<<ETX>>

Integrating CAM and process simulation to enhance on-line analysis and control of IC fabrication

The integration of a process simulator with a commercial computer-aided manufacturing (CAM) system to provide a set of powerful tools for process analysis, diagnosis, and control is described. The CAM system acts as the interface to the simulator and maintains the simulation control data as part of the process specification. Making process simulation available in a manufacturing environment allows engineers to intuitively investigate the process, thus aiding their understanding of the interrelation of process steps. A microprocessing scenario in an application-specific integrated circuit (ASIC) facility is used to demonstrate how the system can be used to analyze options for corrective processing. It can also be used for documenting processes, to simplify process transfer and implementation, and for investigating the effect of corrective processing on device reliability. >

An interconnect scheme for reducing the number of contact pads on process control chips

An approach is presented to reduce the number of pads required by electrical test structures by using a multiplexed interconnect scheme. This passive multiplexed scheme requires only two levels of interconnect and can be used for transistors, electrical verniers, yield monitoring, reliability evaluations, continuity tests, and measuring the resistance of tracks. The basic measurement procedure to access individual components is to force a voltage on one of the access pads and then ground one of the group terminals via an ammeter. While an even number of pads is not mandatory it is recommended since this maximizes the efficiency of pad usage. >

/spl Delta/L Extraction Using Parasitic Bipolar Transistors

If l/p is then plotted against L,, the intercept of the best fit straight line with the L, axis is 2AL. It is important that the drain voltage is kept low so that there is no depletion layer around the drain which would increase the measured value of AL. The gate voltage must be high enough to operate the transistor in the linear region, in order to maximise p and reduce the influence of parasitic source and drain contact resistances. The accuracy of this method is largely determined by the measurement made on the smallest drawn length transistor. Short channel effects such as the modulation of V , give rise to increased values of P being calculated and a consequent reduction in the accuracy of the measurement. The proposed use of lateral bipolar transistors avoids these inherent errors.

Photoresist dissolution rates: a comparison of puddle, spray, and immersion processes

Design and operation of an on-line Track Development Rate Monitor (TDRM) for track development systems are described. Dissolution data, measured using this equipment, for spray and puddle development processes is presented and compared to those derived from a conventional immersion DRM. Immersion data has traditionally been used to model all development. The validity of this is discussed. Also presented is an off-line technique for evaluating dissolution rates which utilize no specialized DRM equipment. The dissolution rates as measured by this technique are compared with those obtained from the TDRM/DRM methods. Simulations using all the calculated dissolution parameters are compared with SEM cross sections so that a practical evaluation of the various techniques can be made.