G. Bodammer

Functional and spatial segregation of secretory vesicle pools according to vesicle age

Synaptic terminals and neuroendocrine cells are packed with secretory vesicles, only a few of which are docked at the plasma membrane and readily releasable. The remainder are thought to constitute a large cytoplasmic reserve pool awaiting recruitment into the readily releasable pool (RRP) for exocytosis. How vesicles are prioritized in recruitment is still unknown: the choice could be random, or else the oldest or the newest ones might be favoured. Here we show, using a fluorescent cargo protein that changes colour with time, that vesicles in bovine adrenal chromaffin cells segregate into distinct populations, based on age. Newly assembled vesicles are immobile (morphologically docked) at the plasma membrane shortly after biogenesis, whereas older vesicles are mobile and located deeper in the cell. Different secretagogues selectively release vesicles from the RRP or, surprisingly, selectively from the deeper cytoplasmic pool. Thus, far from being equal, vesicles are segregated functionally and spatially according to age.

Evaluation of sheet resistance and electrical linewidth measurement techniques for copper damascene interconnect

The effects of the barrier layer and dishing in copper interconnects lead to extra difficulties in measuring sheet resistance (R/sub S/) and linewidth when compared with equivalent measurements on nondamascene tracks. This paper examines these issues and presents the results of simulations that quantify the effects of diffusion barrier layers and dishing on the extraction of R/sub S/ from cross type test structures and the effect this has on linewidth measurement.

Review of the history and technology of micromachined miniature displays using foundry-produced silicon backplanes

Liquid-crystal over silicon is an established technology for reflective spatial light modulators and microdisplays. This paper reviews their development to date, highlighting in particular the micromachining of the mirror array and the associated packaging issues.

Evaluation of the issues involved with test structures for the measurement of sheet resistance and linewidth of copper damascene interconnect

The effect of the barrier layer and dishing in copper interconnects causes extra difficulties in measuring sheet resistance and linewidth when compared with equivalent measurements on nondamascene processed tracks. This paper examines these issues and, for the first time, quantifies the effects of diffusion barrier layers and CMP dishing on the extraction of R/sub s/ from Greek cross type structures and the effect this has on linewidth measurement.

Microfabrication and packaging of deformable mirror devices

We describe the fabrication and testing of deformable membrane mirrors over silicon backplanes using our in-house CMOS processing facilities. The fabrication of dense arrays of electrostatic actuators on the backplane potentially allows fine control of the membrane surface shape than can be produced when using a printed circuit board as the backplane. We presents a range of techniques for fabrication the membrane mirrors in various materials and mating the structure to a silicon backplane. We characterise membrane deflection with electric field for silicon nitride and polymer membranes over a passive silicon backplane consisting of 37 directly-addressed electrode pads configured in a hexagonal array.

26.3: Investigation of the Bow of Silicon Backplanes for Microdisplay Applications

The optical performance of ferroelectric liquid crystal over silicon (FLCOS) microdisplay devices can be greatly improved by ensuring that the silicon backplane that forms the core of the display engine is both smooth and flat. In this paper we investigate the effect of the circuit design and manufacturing process on the bow of the silicon CMOS drive circuitry.

Microdisplay Packaging Challenge

The packaging of ferro-electric liquid crystal over silicon (FLCOS) microdisplays presents itself as a formidable challenge to the package designer. The overall assembly should be lightweight, rugged, and incorporate the display engine, the illumination unit and the viewing optics. Good optical performance of the displays depends on many variables that need to be optimised. The silicon chip acts as part of an optical device and so standard packaging procedures are not readily applicable. In particular, the silicon chip requires significant post-processing to ensure it is both smooth and flat even after assembly. Selection of a suitable packaging strategy is key to success. In this paper we evaluate various methods of first level packaging of the silicon display engine.

Alignment of ferroelectric liquid crystals over CMOS-based microdisplay backplanes

Defect free homogeneous alignment of ferroelectric liquid crystals in the surface stabilized configuration remains challenging to obtain even over the relatively small area of liquid crystal on silicon microdisplays. The limitations of the conventional rubbed polymer alignment technique are discussed and the benefits brought by recent advances in backplane post-processing are demonstrated in realistic conditions. The potential of the linearly photopolymerized photoalignment technique are highlighted in terms of alignment quality, susceptibility to zigzag defects, and electro-optical performances.

Fabrication of spatial light modulator backplanes using damascene processing

The alignment of ferroelectric liquid crystal (FLC) is heavily influenced by the FLC flow rate during SLM cell filling. This flow rate is affected by a number of factors, one aspect of which is the structure of the silicon backplane. Even when the device has been planarized the structure of the pixelated top layer metal still influences the FLC flow rate and therefore the FLC alignment. We have produced a flat silicon backplane substrate using damascene processing to manufacture the mirror/electrodes. Damascene processing is a metal polishing technique. In this process the oxide layer which has already been polished is etched to create trenches in the desired pattern of the metal layer, a blanket deposition of metal is then performed, which fills the trenches and covers the wafer surface, finally CMP is performed, which removes the excess material on the wafer surface leaving the metal in the trenches and the top surface flat. There are some problems associated with damascene processing which will affect its suitability in the micro-=fabrication of SLM backplanes. The softer metal material is prone to dishing and scratching and the harder oxide material can be eroded. THese effects are dependent on the level of control of the CMP process. A process is being developed, using novel slurry chemistries, to allow the incorporation of this technique into our post-processing procedure. The results of the application of this process to test structures and an analysis of the suitability of this technique in the microfabrication of SLM silicon backplanes will be presented.

Ferroelectric liquid crystal over active silicon technology for displays

The structure and principle of operation of a ferroelectric liquid crystal - over - CMOS silicon display are described. Several addressing schemes for creating full color images are introduced and assessed. Preliminary results using 176 X 176 pixel and 512 X 512 pixel DRAM displays are presented.