L. Carbonell

3D integration by Cu-Cu thermo-compression bonding of extremely thinned bulk-Si die containing 10 μm pitch through-Si vias

Using standard single damascene type techniques on bulk-Si, combined on one hand with extreme wafer thinning and on the other with Cu-Cu thermo-compression bonding technology, the paper demonstrate yielding 10k through-wafer 3D-via chains with a via pitch of 10μm for a via diameter of 5μm. The bonded contacts exhibit shear strengths exceeding 40MPa. Measurements indicate there is no significant contact resistance at the Cu-Cu bonded interface: within measurement accuracy, the 4-point via chain resistance is consistent with bulk Cu resistivity

High Q inductor add-on module in thick Cu/SiLK/sup TM/ single damascene

Thick Cu single damascene inductors with very high Q factors are integrated on top of a standard aluminum 3LM BEOL process. Obtained Q factors are more than four times higher than Q factors of the inductors of the same geometry processed in the Al 3LM BEOL. For an inductor of 2.8 nH inductance, a Q peak of 24 at 2 GHz was reached by using 4 /spl mu/m thick Cu on a 2 /spl mu/m IMD oxide layer.

Corrosion inhibition by self-assembled monolayers for enhanced wire bonding on Cu surfaces

Corrosion inhibition by thiol-derived self-assembled monolayers (SAMs) on Cu surfaces has been characterised using contact angle measurements, X-ray photoelectron spectroscopy, voltammetry, and thermal desorption spectroscopy. Factors influencing SAM formation were investigated to develop an optimised wafer level process. XPS confirms the formation of thiolate species bonded to a mixed metallic Cu and cuprous oxide surface. Stability studies as a function of temperature and electrochemical potential demonstrate promising passivation properties. The feasibility of exploiting SAMs in microelectronics applications was demonstrated by the enhancement of Cu wire bonding onto Cu bond pads.

Influence of absorbed water components on SiOCH low-k reliability

We investigated plasma treatment induced water absorption in a SiOCH low-k dielectric and the influence of the absorbed water components on the low-k dielectric reliability. By using thermal desorption spectroscopy (TDS), water absorption in SiOCH was evidenced for N2/H2 plasma treatments. Based on these TDS results, two anneal temperatures were selected to separate and quantify the respective contributions of two absorbed water components, physisorbed (α) and chemisorbed (β) water, to low-k dielectric reliability. With the physisorbed water desorbed by an anneal at 190 °C, the low-k dielectric shows reduced leakage currents and slightly improved time-dependent dielectric breakdown (TDDB) lifetimes. However, the observed failure mechanism represented by the TDDB thermal activation energy (Ea) does not change until the chemisorbed water component was desorbed by an anneal at 400 °C. The close similarity between Ea and the bond energy associated with the β water component demonstrates that the β bond is amo...

Au-Free AlGaN/GaN Power Diode on 8-in Si Substrate With Gated Edge Termination

High-performance AlGaN/GaN diodes are realized on 8-in Si wafers with Au-free CMOS-compatible technology. The diodes are cointegrated on the same substrate together with the AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors and with only one extra lithographic step. The diode anode and the transistor gate are processed together and the same metallization is used for both, avoiding extra metal deposition dedicated to the Schottky junction. A gated edge termination allows obtaining low reverse leakage current (within 1 μA/mm at -600 V), which is several orders of magnitude lower than the one of conventional Schottky diodes processed on the same wafer. Recess is implemented at the anode, resulting in low diode turn-on voltage values.

Post patterning meso porosity creation: a potential solution for pore sealing

The creation of meso porosity in single damascene structures after patterning has been investigated to facilitate the sealing of the sidewalls by iPVD barriers. The dielectric stack consists of developmental porous SILK (v7) resin (SiLK is a trademark of The Dow Chemical Company) and a chemical vapor deposited hard mask. Porous SILK (v7) resin was selected since the temperature of vitrification of the material is lower than the temperature of porogen burn out. Creation of meso porosity after patterning results in smooth trench sidewalls, leading to an improved iPVD barrier integrity, as opposed to the conventional process sequence, which gives rise to large, exposed pores at the sidewall.

Characterisation and integration feasibility of JSR's low-k dielectric LKD-5109

Increasing the circuit density is driving the need for lower permittivity interlayer dielectrics (ILD) to reduce the capacitance between long parallel lines. JSRs LKD-5109, an MSQ-based material, is one of such low-k materials for the 65-nm node. The feasibility of integrating LKD-5109 in a single inlaid structure has been investigated. Thermal stability, chemical compatibility to stripping agents and CMP slurries are verified. A single damascene structure incorporating a dual CVD hard mask has been attempted and electrical results have been evaluated.

Bulk Properties of MOCVD-Deposited HfO2 Layers for High k Dielectric Applications

The physical bulk properties of metalorganic chemical vapor deposited (MOCVD) deposited HfO 2 layers were characterized as a function of deposition temperature. thickness, and starting surface. It is shown that depositing HfO 2 layers at 300°C results in a lower density film compared to films deposited at higher temperature (e.g., 485 and 600°C). In addition, it is shown that layers deposited at 300°C contain significant amounts of carbon originating from the organic precursor (tetrakis-diethylamidohafnium). As a result of the low density and/or carbon contamination, the dielectric properties of these layers are very poor. It is observed that the density of the film is heavily dependent on the thickness, where very thin layers have a density that is only a fraction of the bulk density regardless of the deposition temperature. For thicker layers, a higher deposition temperature is seen to result in a higher density, although still lower than bulk density, as observed by ellipsometric porosimetry. Finally, the crystalline state of the material is found to be dependent on the deposition temperature, thickness, and post-deposition anneal. Based on our results, MOCVD deposited HfO 2 layers are expected to be polycrystalline and present in its cubic and/or monoclinic phase.

Scalability of plasma enhanced atomic layer deposited ruthenium films for interconnect applications

Ru thin films were deposited by plasma enhanced atomic layer deposition using MethylCyclopentadienylPyrrolylRuthenium (MeCpPy)Ru and N2/NH3 plasma. The growth characteristics have been studied on titanium nitride or tantalum nitride substrates of various thicknesses. On SiO2, a large incubation period has been observed, which can be resolved by the use of a metal nitride layer of ∼ 0.8 nm. The growth characteristics of Ru layers deposited on ultra-thin metal nitride layers are similar to those on thick metal nitride substrates despite the fact that the metal nitride layers are not fully closed. Scaled Ru/metal nitride stacks were deposited in narrow lines down to 25 nm width. Thinning of the metal nitride does not impact the conformality of the Ru layer in the narrow lines. For the thinnest lines the Ru deposited on the side wall showed a more granular structure when compared to the bottom of the trench, which is attributed to the plasma directionality during the deposition process.

On a More Accurate Assessment of Scaled Copper/Low-k Interconnects Performance

Interconnect RC delay, predominantly affected by the effective dielectric constant (k-value) and by the copper resistivity (rhoCu), is an important performance metric for back-end-of-line (BEOL) process assessment. As process technology scales, interpretation of fundamental process-induced RC delay variations becomes a challenge as the relative importance of statistical process-induced fluctuations (variation of critical dimensions during plasma etching of low-k materials, line profiles, thickness nonuniformity, etc.) grows rapidly and begins to show. A more accurate interpretation of experimental data and prediction of future performance trends requires a more realistic assessment that accounts for such statistical fluctuations. In this paper, an inventory of the most common possible sources of statistical process-induced RC delay variations is made, parameterized, and subsequently used to generate a realistic 2-D interconnect model from which, R and C, and thereby RC delay, are computed. For both wire resistivity and RC, response surface models (RSM) are subsequently generated based on the results of a full factorial design-of-experiment analysis with these input parameters. Finally, based on the RSMs, an improved methodology of interconnect performance evaluation is proposed.