Bram Sijmus

Low leakage high breakdown e-mode GaN DHFET on Si by selective removal of in-situ grown Si 3 N 4

We describe the fabrication and characteristics of high voltage enhancement mode SiN/AlGaN/GaN/AlGaN double heterostructure FET devices. The Si3N4 not only acts as a passivation layer but is crucial in the device concept as it acts as an electron donating layer (1). By selective removal under the gate of the in-situ SiN, we realize e-mode operation with a very narrow threshold voltage distribution with an average value of +475 mV and a standard deviation of only 15 mV. Compared to the reference depletion mode devices, we see no impact of the e-mode architecture on the breakdown behaviour. The devices maintain very low leakage currents even at drain biases up to 80% of the breakdown voltage.

Characterisation and integration feasibility of JSR's low-k dielectric LKD-5109

Increasing the circuit density is driving the need for lower permittivity interlayer dielectrics (ILD) to reduce the capacitance between long parallel lines. JSRs LKD-5109, an MSQ-based material, is one of such low-k materials for the 65-nm node. The feasibility of integrating LKD-5109 in a single inlaid structure has been investigated. Thermal stability, chemical compatibility to stripping agents and CMP slurries are verified. A single damascene structure incorporating a dual CVD hard mask has been attempted and electrical results have been evaluated.

Impact of LKD5109 TM low- k to cap/liner interfaces in single damascene process and performance

The importance of interface quality in the single damascene integration process of LKD5109TM porous low-k films is investigated. A strong correlation is observed between chemical mechanical planarization (CMP) performance and LKD/cap layer interfacial fracture energies. The use of FF02TM as cap layer material (an on-purpose developed spin-on organic hard-mask) on LKD leads to superior interfacial adhesion and metal continuity yield as compared to the use of chemical vapour deposition SiC:H cap films. The adhesion quality of LKD/liner films appears less critical than LKD/cap layer adhesion as far as CMP performance is concerned. Electrical line-to-line performance is not always directly correlated with adhesion but rather, more generally speaking, with interface quality (i.e., presence of defects/dangling bonds or moisture). The introduction of surface pre-treatments to enhance interfacial adhesion leads to degradation in both leakage current and breakdown field behaviour because of damage induced at the interface.

Integration feasibility of porous SiLK* semiconductor dielectric

The feasibility of integrating a SiLK* Semiconductor Dielectric film (*trademark of The Dow Chemical Company) that contains closed pores was studied using a single damascene test vehicle. The study focussed on tool qualification, process set-up and single damascene feasibility to demonstrate technology extendibility. The results indicate that only minor changes have to be made to the process conditions when transitioning from a dense to a porous SiLK* film.

GaN-on-Si power field effect transistors

GaN-on-Si has become the most promising technology for next-generation power switching devices to overcome intrinsic Si limits for high temperature operation, high efficiency at high operating voltage, and high switching frequency. Depletion-mode devices are already offering more than one order of magnitude lower specific on-resistance above 600V. Further, we have recently demonstrated e-mode devices (Vt>0.5V) with high current density, thanks to a unique in-situ SiN passivation approach. This in-situ SiN layer is further shown to be a key parameter for device stability at elevated temperatures, significantly enhancing the device reliability in high temperature accelerated lifetime tests.

Integration of Single Damascene 85/85 nm L/S copper trenches in Black Diamond using 193 nm optical lithography with dipole illumination

This paper describes the integration of Single Damascene 85/85 nm L/S copper trenches in Black Diamond (Applied Materials) dielectric (k=2.85). Optical lithography (193 nm) with off-axis illumination was used to print the trenches. Integration issues are discussed, and resistance and RC delay data are presented. The method is applied to study the resistivity for sub 100 nm copper lines.

(Invited) Epitaxial Growth of III-Nitrides on Silicon Substrates

Hetero epitaxial structures with strained layers are widely used in electronic and optoelectronic semiconductor devices. Over the last decades the group III-Nitride semiconductor materials have been extensively used for light emitting applications and are nowadays emerging as promising candidates for high power electronic applications. Unlike the “classical” semiconductor materials (based on Si, Ge, GaAs, InP), group III-Nitrides crystallize in the wurtzite structure and thus have a hexagonal lattice. Furthermore, as no native substrates are available for the III-Nitrides, growth is performed on foreign substrates such as sapphire, siliconcarbide or silicon. III-Nitride epi layers grown on silicon substrates offer a lower cost technology compared to other substrates because of the scalability towards larger wafer size and the leveraging on Si technology. However, the large thermal and lattice mismatch between IIINitrides and silicon requires advanced deposition schemes to allow compensating for the huge tensile thermal stresses and to reduce the dislocation density in these materials. In the early nineties, high quality GaN has been first demonstrated on sapphire substrates. The use of low temperature AlN or GaN nucleation layers strongly improved the crystalline quality. A three-dimensional (3D) to two-dimensional (2D) transition was observed during the high temperature GaN growth on top of a low temperature nucleation layer. It was found that better crystalline quality could be achieved if the coalescence process was intentionally delayed using either low V/III ratio or relatively high pressure controlling as such the density and size of nuclei in the nucleation layer. However, the dislocation density in hetero epitaxial GaN layers is still rather large, in the range of 10 /cm. A further reduction of the dislocation density can be obtained by applying epitaxial lateral overgrowth (ELOG) AlN or AlN/SixNy inter layers. In the last decade, GaN-on-Si has received a lot of attention and exciting results have been demonstrated. The large thermal and lattice mismatch between GaN epitaxial layers and Si substrates lead to severe wafer bowing and even cracking of the epitaxial GaN layers, however low temperature AlN interlayers, Al(Ga)N/GaN superlattices and AlGaN inter layers have been applied to compensate the large thermal tensile stress in the GaN layers imposed by the Si substrate in order to prevent the generation of cracks. Many difficulties still remain, notably in obtaining the highest GaN material quality with respect to (extended) defect density and unintentional background impurity levels. Control of these properties is essential to improve device performance. We have shown that it is possible to grow thick semi-insulating GaN layers on Si(111) substrates with symmetric (0002) peak FWHM as low as 600 arcsec and asymmetric (1-102) peaks as narrow as 830 arcsec. This requires growth temperatures of 1130°C or above (see figure 1). SIMS measurements reveal that carbon is the major impurity in our GaN layers but the concentration can be decreased to well below 10cm, when using sufficiently high growth temperature. Low-temperature PL shows that in such layers no defect-related transitions occur. These defectfree GaN layers have a very high resistivity of beyond 10Ωcm and are thus suitable as buffer layers in dispersion free HEMT devices. In samples grown at temperatures below 1100°C, both Blue Luminescence (BL) and Yellow Luminescence (YL) were observed. The BL band can be attributed to the DAP transition involving recombination via CGa–CN. The YL could originate either from carbon complexes Ci–CGa or Ci–CN, as in our samples the dominant unintentionally incorporated impurity is carbon. Alternatively, the YL is due to the VGa–ON complex localized on edge-type dislocations and would then be of similar origin as the YL band in n-type GaN grown on sapphire substrates.

New Slurry Formulation for Copper-CMP Process in a Damascene Integration Scheme

In this work novel slurries both for copper and tantalum nitride removal were developed. In the first step the Cu bulk is removed, by using high selective slurry, which stops on the underlying TaN barrier. The selectivity of Cu vs. TaN achieved with this slurry is larger than 1/100. High selective second step slurry is further introduced for removing the barrier material. In the present work data concerning dishing and erosion will be presented as a function of line width and pattern density across the wafer. Electrical yield measurements on shorts and opens of meander-fork structures will be discussed.