J.Y.-C. Sun

75-GHz f/sub T/ SiGe-base heterojunction bipolar transistors

The fabrication of silicon heterojunction bipolar transistors which have a record unity-current-gain cutoff frequency (f/sub T/) of 75 GHz for a collector-base bias of 1 V, an intrinsic base sheet resistance (R/sub bi/) of 17 k Omega / Square Operator , and an emitter width of 0.9 mu m is discussed. This performance level, which represents an increase by almost a factor of 2 in the speed of a Si bipolar transistor, was achieved in a poly-emitter bipolar process by using SiGe for the base material. The germanium was graded in the 45-nm base to create a drift field of approximately 20 kV/cm, resulting in an intrinsic transit time of only 1.9 ps.<<ETX>>

Si/SiGe epitaxial-base transistors. I. Materials, physics, and circuits

A detailed review of SiGe epitaxial base technology is presented, which chronicles the progression of research from materials deposition through device and integration demonstrations, culminating in the first SiGe integrated circuit application. In part I of this paper, the requirements and processes for high-quality SiGe film preparation are discussed, with emphasis on fundamental principles. A detailed overview of SiGe HBT device design and implications for circuit applications is then presented. >

Si/SiGe epitaxial-base transistors. II. Process integration and analog applications

For pt. I, see ibid., vol. 3, p. 455-68 (1995). This part focuses on process integration concerns, first described in general terms and then detailed through an extensive review of both simple non-self-aligned device structures and more complex self-aligned device structures. The extension of SiGe device technology to high levels of integration is then discussed through a detailed review of a full SiGe HBT BiCMOS process. Finally, analog circuit design is discussed and concluded, with a description of a 12-bit Digital-to-Analog Converter presented to highlight the current status of SiGe technology. >

A high-performance 0.25- mu m CMOS technology. II. Technology

For Pt. I, see ibid., vol.39, no.4, pp.959-966 (1992). The key technology elements and their integration into a high-performance, selectively scaled, 0.25- mu m CMOS technology are presented. Dual poly gates are fabricated using a process where the poly and source/drain (S/D) are doped simultaneously. The critical issues related to the dual poly gate are addressed. A reduced operating voltage of 2.5 V is used which allows the application of shallow junctions with abrupt profiles (no LDD) to minimize the device series resistance as well as gate to source/drain overlap capacitance. The poly gate and the S/D sheet resistances are lowered, using a thin salicide (TiSi/sub 2/) process. The TiSi/sub 2/ thickness is reduced to maintain low leakage and low contact resistance for the shallow S/D junctions. The gate level with 0.4- mu m physical length is defined using optical lithography with a contrast enhanced layer (CEL) resist system. >

On the profile design and optimization of epitaxial Si- and SiGe-base bipolar technology for 77 K applications. I. Transistor DC design considerations

The DC design considerations associated with optimizing epitaxial Si- and SiGe-base bipolar transistors for the 77-K environment are examined in detail. Transistors and circuits were fabricated using four different vertical profiles, three with a graded-bandgap SiGe base, and one with a Si base for comparison. All four epitaxial-base profiles yield transistors with DC properties suitable for high-speed logic applications in the 77-K environment. The differences between the low-temperature DC characteristics of Si and SiGe transistors are highlighted both theoretically and experimentally. A performance tradeoff associated with the use of an intrinsic spacer layer to reduce parasitic leakage at low temperatures and the consequent base resistance degradation due to enhanced carrier freeze-out is identified. Evidence that a collector-base heterojunction barrier effect severely degrades the current drive and transconductance of SiGe-base transistors operating at low temperatures is provided. >

On the accuracy of channel length characterization of LDD MOSFET's

A comprehensive investigation into the various mechanisms that limit the accuracy of channel length extraction techniques for lightly doped drain (LDD) MOSFETs is presented. Analytic equations are derived to quantify the sensitivity of the extraction techniques to the geometry effect, and bias dependence of the n-source and drain resistance. The analytic approach is supplemented and verified by exercising channel length extraction algorithms on current-voltage characteristics obtained from rigorous numerical simulations of a variety of LDD MOSFETs. The analyses clearly show that low gate overdrives and consistent threshold voltage measurements are required to accurately extract the metallurgical channel length. The analytic equations can be used to project the limitations of channel length extraction methods for future submicrometer LDD MOSFETs.

Characteristics of SOI FET's under pulsed conditions

A system for measuring output characteristics of FETs using nanosecond pulses, instead of dc voltage and current measurement, is described. The measurement system is used to obtain the I-V characteristics of silicon-on-insulator (SOI) FETs without the degradation resulting from self heating. Use of the technique to study partially depleted SOI FETs with floating bodies shows that under pulsed conditions, their output curves have a history dependence. The physical mechanisms responsible for the history dependence are explained. Further understanding of the physical mechanisms is given by examination of single-shot pulse measurements. The role of transient and time-dependent phenomena in determining I-V curves is elucidated.

Measurement of I-V curves of silicon-on-insulator (SOI) MOSFET's without self-heating

A new method for measuring the output (I/sub D/-V/sub D/) characteristics of SOI MOSFETs without self-heating is described. The method uses short pulses with a low repetition rate, and a reverse transient loadline construction. The technique is demonstrated by measuring 0.25 /spl mu/m bulk and SOI MOSFETs with 5-nm gate oxide. Application of the method to the extraction of device temperature as a function of DC power is also illustrated.<<ETX>>

73-GHz self-aligned SiGe-base bipolar transistors with phosphorus-doped polysilicon emitters

The authors report a thermal-cycle emitter process using phosphorus for the fabrication of self-aligned SiGe-base heterojunction bipolar transistors. The low thermal cycle results in extremely, narrow basewidths and preservation of lightly doped spacers in both the emitter-base and base-collector junctions for improved breakdown. Transistors with 35-nm basewidths were obtained with low emitter-base reverse leakage and a peak cutoff frequency of 73 GHz for an intrinsic base sheet resistance of 16 k Omega / Square Operator . Minimum NTL (nonthreshold logic) and ECL (emitter-coupled logic) gate delays of 28 and 34 ps, respectively were obtained with these devices.<<ETX>>

Identification of perimeter depletion and emitter plug effects in deep-submicrometer, shallow-junction polysilicon emitter bipolar transistors

Two new types of narrow-emitter effects are identified in shallow and narrow-junction polysilicon emitter bipolar transistors. These effects result from a lower doping concentration close to the emitter perimeter of large devices (perimeter depletion effect) or in very-narrow-emitter devices where the polysilicon plugs up the emitter window (emitter plug effect). The consequence is a locally shallower emitter junction which causes a reduced collector current density and a nonideal base current due to a partial overlap of the emitter-base space-charge region with the poly/monosilicon interface. The nonuniform doping in the polysilicon is verified by energy-dispersive X-ray spectroscopy (EDX) measurements. Electrical measurements give a clear indication of the emitter plug effect for two different self-aligned transistor structures, and further evidence is given by a comparison of various poly emitter processes. >