Ja-Chun Ku

Highly productive PCRAM technology platform and full chip operation: Based on 4F 2 (84nm pitch) cell scheme for 1 Gb and beyond

We successfully developed highly scalable and cost-effective PCRAM technology based on 0.007um2 (4F2, 84nm pitch) sized novel cell scheme. The chip size and density are 33.207mm2 and 1Gb. The device functionality and reliability were clearly demonstrated through fully integrated chip, which showed a promising feasibility for productive NVM applications.

Gate Oxide Reliability Characterization of Tungsten Polymetal Gate with Low-Contact-Resistive WSix/WN Diffusion Barrier in Memory Devices

Gate oxide reliability characteristics using different diffusion barrier metals for a tungsten polycrystalline silicon (poly-Si) gate stack were investigated in detail. The insertion of a thin WSix layer in a tungsten poly gate stack could effectively relieve the mechanical stress of a gate hardmask nitride film during a post thermal process, which contributes to better gate oxide reliability and the stress-immunity of the transistor. This insertion could also prevent the formation of a Si–N inter-dielectric layer, which could lower the contact resistance between poly and tungsten effectively. A W/WN/WSix/poly gate stack could be a promising candidate for a future W poly gate that shows reliable high-speed characteristics in dynamic random access memory applications.

Novel shallow trench isolation process using flowable oxide CVD for sub-100 nm DRAM

We have investigated the characteristics of cell leakage and data retention time when using flowable oxide chemical vapor deposition (CVD) as a shallow trench isolation (STI) process of 1-Gbit DRAM. The trench gap filling capability was increased dramatically by combining high-density plasma (HDP) CVD with flowable oxide CVD. The reduced local stress by flowable oxide in narrow trenches leaded to decrease in junction leakage and gate induced drain leakage (GIDL) current and increase in data retention time of DRAM compared to HDP STI. Therefore, it is concluded that the combination of flowable oxide and HDP oxide is the most promising technology for STI gap filling process of sub-100 nm DRAM technology.

Plasma enhanced chemical vapor deposition Si-rich silicon oxynitride films for advanced self-aligned contact oxide etching in sub-0.25 μm ultralarge scale integration technology and beyond

We intentionally introduced excessive Si during the SiOxNy film deposition in order to increase the etch selectivity-to-SiOxNy for advanced self-aligned contact (SAC) etching in sub-0.25 μm ultralarge scale integration devices. The SiOxNy layer was deposited at a conventional plasma enhanced chemical vapor deposition chamber by using a mixture of SiH4, NH3, N2O, and He. The gas mixing ratio was optimized to get the best etch selectivity and low leakage current. The best result was obtained at 10% Si–SiOxNy. In order to employ SiOxNy film as an insulator as well as a SAC barrier, the leakage current of SiOxNy film was evaluated so that SiOxNy may have the low leakage current characteristics. The leakage current of 10% Si–SiOxNy film was 7×10−9 A/cm2. Besides, the Si-rich SiOxNy layer excellently played the roles of antireflection coating for word line and bit line photoresist patterning and sidewall spacer to build a metal–oxide–semiconductor transistor as well as a SAC oxide etch barrier. The contact oxid...

Influence of Hydrogen Incorporation on the Reliability of Gate Oxide Formed by Using Low-Temperature Plasma Selective Oxidation Applicable to Sub-50-nm W-Polymetal Gate Devices

This letter reveals the physical and electrical properties of silicon dioxide (Si02) formed by the plasma selective oxidation (plasma selox) using 02 and H2 gas mixture, which is applicable to sub-50-nm tungsten-polymetal gate memory devices without capping nitride film. Metal-oxide-semiconductor capacitors with gate oxide formed by the plasma selox at the process temperature in the range of 400degC-700degC showed much better time-dependent dielectric-breakdown characteristics than those formed by the conventional thermal selox at 850degC. On the other hand, in the case of very low temperature (25degC) plasma selox, the gate oxide degradation such as initial breakdown was found. It turned out to be due to the excessive hydrogen and water incorporation into the SiO2 layer through thermal desorption spectroscopy measurements.

Low resistive tungsten dual polymetal gate process for high speed and high density memory devices

We developed ultra-low resistive tungsten dual polymetal gate memory device by using Ti-based diffusion barrier and a unique tungsten chemical vapor deposition (CVD) process with B2H6-based nucleation layer. The low resistive CVD-W (LRW) polymetal gate process not only reveals good gate oxide reliability comparable to PVD-W process, but also highly improved transistor performances such as signal delay characteristics.

Integration of Low Resistive CVD-W Interconnects for sub-50nm FEOL application

Low resistive tungsten (LRW) interconnects using CVD-W films deposited on B2H6-reduced W nucleation layers have been successfully developed for FEOL application of sub-50nm dynamic random access memory (DRAM). LRW poly-metal gate showed excellent gate oxide integrity, low sheet resistance, low parasitic capacitance, and excellent transistor performances such as ring-oscillator delay comparable to PVD-W based poly-metal gate. In the bit line application, as the feature size was decreased, the contact resistance and sheet resistance of LRW bit line were decreased drastically compared to conventional CVD-W process. However, the properties of junction leakage current and saturation drain current (Idsat) of NMOS transistor were degraded due to the penetration of boron into the junction. In order to depress the junction degradation, the improvement of barrier properties of glue-layer and optimization of LRW process were suggested.

Study on the Effect of RTA Ambient to Shallow N+/P Junction Formation using PH3 Plasma Doping

Plasma doping (PLAD) process utilizing PH3 plasma to fabricate n-type junction with supplied bias of −1 kV and doping time of 60 sec under the room temperature is presented. The RTA process is performed at 900 °C for 10 sec. A defect-free surface is corroborated by TEM and DXRD analyses, and examined SIMS profiles reveal that shallow n+ junctions are formed with surface doping concentration of 10 21 atoms/cm 3 . The junction depth increases in proportion to the O 2 gas flow when the N 2 flow is fixed during the RTA process, resulting in a decreased sheet resistance. Measured doping profiles and the sheet resistance confirm that the n+ junction depth less than 52 nm and minimum sheet resistance of 313 Ω/□ are feasible.

Improved Re‐Crystallization of p+ Poly‐Si Gates with Molecular Ion Implantation

Implantation of B18H22 molecules at 80 keV and doses up to 4×1016 cm−2 were evaluated for the application of p‐type counterdoping of in situ n‐type doped polysilicon gates. Compared to conventional B implants, molecular implantation provides greatly improved throughput without the risk of energy contamination. Implants at these high doses resulted in poor re‐crystallization of the polysilicon layer due to the formation of excessive cluster‐type defects. Subjecting the polysilicon to either UV‐curing or low temperature soak annealing prior to dopant activation was not effective in improving the re‐crystallization process. However, breaking the dose into two portions at two different energies was shown to significantly improve re‐crystallization of the polysilicon layer. Improved dopant activation was confirmed by a >90% reduction in ring oscillator delay time on a 60 nm PMOSFET.

BEOL process integrations with Cu/FSG wiring at 90 nm design-rule DDR DRAM and their effects on yield, refresh time, and wafer-level reliability

For the first time, this paper presents the results of successful integrations of Cu wiring into a production 512 Mb/90 nm design-rule stacked capacitor and recessed gate DDR (double data rate) DRAM technology, focusing on the effects of Cu integration on DRAM performance, yield, refresh time, and wafer-level reliability. 2 levels Cu interconnect (Ml single damascene and M2 dual damascene) and CVD low-k (FSG) materials have been implemented. Both the reduction in parasitic capacitance and line resistance were found to improve the operation speed of DRAM. No degradation was observed in view of normalized refresh time and yield with Cu wiring. The reliability issues with Cu integration to DRAM were systematically evaluated. In conclusion, this study demonstrates that the Cu wiring is fully compatible with the conventional DRAM and will be expected to meet the requirements of high-performance and high-speed advanced DRAM beyond sub-50 nm node.