Ja Hans Hegt

A 14 bit 200 MS/s DAC With SFDR >78 dBc, IM3 < -83 dBc and NSD <-163 dBm/Hz Across the Whole Nyquist Band Enabled by Dynamic-Mismatch Mapping

This paper presents a 14 bit 200 MS/s current-steering DAC with a novel digital calibration technique called dynamic-mismatch mapping (DMM). By optimizing the switching sequence of current cells to reduce the dynamic integral nonlinearity in an I-Q domain, the DMM technique digitally calibrates all mismatch errors so that both the DAC static and dynamic performance can be significantly improved in a wide frequency range. Compared to traditional current source calibration techniques and static-mismatch mapping, DMM can reduce the distortion caused by both amplitude and timing mismatch errors. Compared to dynamic element matching, DMM does not increase the noise floor since the distortion is reduced, not randomized. The DMM DAC was implemented in a 0.14 μm CMOS technology and achieves a state-of-the-art performance of SFDR >; 78 dBc, IM3 <; -83 dBc and NSD <; -163 dBm/Hz in the whole 100 MHz Nyquist band.

Sigma-delta modulators operating at a limit cycle

A new type of sigma-delta modulator that operates in a special mode named limit-cycle mode (LCM) is proposed. In this mode, most of the SDM building blocks operate at a frequency that is an integer fraction of the applied sampling frequency. That brings several very attractive advantages: a reduction of the required power consumption per converted bandwidth, an immunity to excessive loop delays and to digital-analog converter waveform asymmetry and a higher tolerance to clock imperfections. The LCMs are studied via a graphical application of the describing function theory. A second-order continuous time SDM with 5 MHz conversion bandwidth, 1 GHz sampling frequency and 125 MHz limit-cycle frequency is used as a test case for the evaluation of the performance of the proposed type of modulators. High level and transistor simulations are presented and compared with the traditional SDM designs.

A 3.3-mW /spl Sigma//spl Delta/ modulator for UMTS in 0.18-/spl mu/m CMOS with 70-dB dynamic range in 2-MHz bandwidth

The authors present a 4th-order continuous-time ΣΔ modulator with 1.5 b quantizer and feedback DAC for a UMTS receiver. The modulator has 70 dB DNR in a 2 MHz band and -74 dB THD at full scale. An IC which includes two modulators, a PLL, and an oscillator dissipates 11.5 mW at 1.8 V. Active area is 0.41 mm/sup 2/ in a 0.18 μm, 1-poly 5-metal-layer CMOS technology.

An 11b Pipeline ADC With Parallel-Sampling Technique for Converting Multi-Carrier Signals

This paper presents a parallel sampling technique for analog-to-digital converters (ADCs) to convert multi-carrier signals efficiently by exploiting the statistical properties of these signals. With this technique, the input signal power of an ADC can be boosted without getting excessive clipping distortion and the ADC can have a higher resolution over the critical small amplitude region. Hence the overall signal to noise and clipping distortion ratio is improved. This technique allows reducing power dissipation and area in comparison to conventional solutions for converting multi-carrier signals. As an example, an 11b switched-capacitor pipeline ADC with the parallel sampling technique applied to its first stage is implemented in CMOS 65 nm technology. It achieves a full-scale input signal range of 2 V differentially with a 1.2 V supply voltage. Simulations show an improvement of more than 5 dB in signal-to-noise-and-clipping-distortion ratio (SNCDR) and around 8 dB in dynamic range (DR) compared to a conventional 11b ADC for converting multi-carrier signals and achieve a comparable SNCDR and noise power ratio (NPR) as a conventional 12b pipeline for converting multi-carrier signals with less than half the power and area.

Statistical Analysis of Mapping Technique for Timing Error Correction in Current-Steering DACs

Timing errors become dominant in dynamic performance of high-speed and high-resolution current-steering digital-to-analog converters (DACs). To improve the dynamic performance and relax the requirements of timing errors in circuit/layout design, a mapping technique, based on on-chip timing error measurement, was proposed. This mapping technique can significantly improve the dynamic performance, no matter if timing errors are interconnection-related or mismatch-related. Matlab simulation results show that the spurious-free dynamic range (SFDR) is improved, e.g. 30dB for linearly distributed interconnection-related timing errors and 10dB for randomly distributed mismatch-related timing errors.

Smart AD and DA converters

In this paper, a concept is proposed to solve the problems related to the embedding of AD and DA converters in system-on-chips, FPGAs or other VLSI solutions. Problems like embedded testing, yield, reliability and reduced design space become crucial bottlenecks in the integration of high-performance mixed-signal cores in VLSI chips. On the other hand, a trend of increasing digital processing power can be observed in almost all these systems. The presented smart approach takes full advantage of this trend in order to solve the before mentioned problems and to achieve true system integration.

Parallel current-steering D/A Converters for Flexibility and Smartness

This paper presents a DAC architecture built on parallel current-steering sub-DAC entities. Two main novelties are explored: flexibility and smartness. Firstly, a number of available operating modes (op-modes) can set the overall DAC performance and functionality. These op-modes transfer some of the important design trade-offs to the end-user and constitute the DAC flexibility. The main examples include: resolution-power-number of DACs, static-dynamic performance, etc. Secondly, specific signal processing techniques become possible. The main examples of such techniques include: full self-calibration, cancellation of harmonic distortion (HD) components, and linearity improvement through redundancy. This paper concentrates on a method to suppress undesired HD components through DA processing of phase shifted replicas of the main input signal. The presented theoretical concepts are realized in a 14-bit DAC built from 4 parallel 12-bit sub-DACs. Transistor simulations and a layout design are also presented. The demonstrated flexibility characteristics of the new DAC architecture make the discussed concepts particularly suitable for FPGA integration.

Digital post-correction of front-end track-and-hold circuits in ADCs

This paper presents the design of a digitally post-corrected open-loop front-end track-and-hold circuit for a pipelined ADC. An open-loop architecture has been selected to achieve high-speed and low power-consumption. Clock-boosting, resistive source-degeneration and cross-coupling are used to reduce low-order harmonic distortion. To further reduce distortion components in the open-loop circuit, a new digital post-correction algorithm is proposed together with a built-in self-measurement technique

A dynamic latched comparator for low supply voltages down to 0.45 V in 65-nm CMOS

This paper presents a dynamic latched comparator suitable for applications with very low supply voltage. It adopts a circuit topology with a separated input stage and two cross-coupled pairs (nMOS and pMOS) stages in parallel instead of stacking them on top of each other as previous works. This circuit topology enables fast operation over a wide input common-mode voltage and supply voltage range. This comparator is designed in 65-nm CMOS technology with standard threshold transistors (VT≈0.4V). Simulation shows that it achieves 5mV sensitivity for a sampling rate of 5GS/s with 1.2V supply voltage, 10mV for 250MS/s with 0.5V supply voltage and 100MS/s with 0.45V supply voltage. The simulated delay time of the proposed comparator is about 30% shorter than the dual-tail dynamic comparator with 0.5V supply voltage and only one third compared to that of the conventional one with 0.6V supply voltage when they are designed to have a similar input referred offset voltage in 65nm CMOS technology.

An 11b pipeline ADC with dual sampling technique for converting multi-carrier signals

This paper presents a dual sampling technique for analog-to-digital converters (ADCs) to convert multi-carrier signals more efficiently and proposes an 11b switched-capacitor pipeline ADC based on this technique. With the dual sampling technique, the input signal power of the ADC can be boosted without getting excessive clipping noise and the ADC can have a higher resolution over the critical low amplitude region. Hence the overall signal to thermal, quantization and clipping noise ratio is improved. The 11b pipeline ADC with the proposed technique achieves a wide input signal range of 2Vppd using a single 1.2V supply. Simulations show an improvement of about 5dB in SNDR and better than 10dB in MTPR compared to a conventional 11b ADC for converting multi-carrier signals.