van Ahm Arthur Roermund

A low-voltage folded-switching mixer in 0.18-/spl mu/m CMOS

Scaling of CMOS technologies has a great impact on analog design. The most severe consequence is the reduction of the voltage supply. In this paper, a low voltage, low power, AC-coupled folded-switching mixer with current-reuse is presented. The main advantages of the introduced mixer topology are: high voltage gain, moderate noise figure, moderate linearity, and operation at low supply voltages. Insight into the mixer operation is given by analyzing voltage gain, noise figure (NF), linearity (IIP3), and DC stability. The mixer is designed and implemented in 0.18-/spl mu/m CMOS technology with metal-insulator-metal (MIM) capacitors as an option. The active chip area is 160 /spl mu/m/spl times/200 /spl mu/m. At 2.4 GHz a single side band (SSB) noise figure of 13.9 dB, a voltage gain of 11.9 dB and an IIP3 of -3 dBm are measured at a supply voltage of 1 V and with a power consumption of only 3.2 mW. At a supply voltage of 1.8 V, an SSB noise figure of 12.9 dB, a voltage gain of 16 dB and an IIP3 of 1 dBm are measured at a power consumption of 8.1 mW.

Analysis and design of an optimally coupled 5-GHz quadrature LC oscillator

A 5-GHz quadrature LC oscillator has been realized, in which the two LC stages are coupled with phase shifters. Analysis on the behavioral level shows that an N-stage LC oscillator is optimally coupled when each stage is connected with phase shifters providing /spl plusmn/180/spl deg//N phase shift. Simulation of the 5-GHz two-stage quadrature LC oscillator reveals a 4.3-dB reduction in phase noise compared to a quadrature LC oscillator without phase shifters. Measurements of the 5-GHz quadrature LC oscillator, made in a 30-GHz f/sub T/ process, show a phase noise lower than -113 dBc/Hz, with a resonator quality factor of only 4 and an oscillator core power dissipation of 21.2 mW.

A GSM/EDGE/WCDMA Adaptive Series-LC Matching Network Using RF-MEMS Switches

To preserve link quality of mobile phones, under fluctuating user conditions, an adaptively controlled series-LC matching circuit is presented for multi-band and multi-mode operation. Following a bottom-up approach, we discuss the design of an RF-MEMS unit cell for the construction of a 5-bit switched capacitor array. To reduce dielectric charging of the RF-MEMS devices their average biasing voltage is minimized by applying a bipolar waveform with a small high/low duty-cycle obtained from a high-voltage driver IC. RF-MEMS capacitive switches are applied because of their high linearity, low loss, large tuning range, and easy control in the discrete domain. Application specific RF-MEMS pull-in and pull-out voltage requirements are derived. An impedance phase detector is used to feed mismatch information to an up-down counter providing robust iterative control. The measured MEMS array capacitance tuning ratio is almost a factor 10. Module insertion loss is 0.5 dB at low-band and high-band. Harmonic distortion is less than -85 dBc at 35 dBm output power and the EVM, measured in EDGE-mode, is less than 1% at 27 dBm . The adaptively controlled module, connected to a planar inverted-F antenna, shows desired impedance correction. For extreme hand-effects the maximum module impedance correction at 900 MHz is -75jOmega.

A 60 GHz Phase Shifter Integrated With LNA and PA in 65 nm CMOS for Phased Array Systems

This paper presents the design of a 60 GHz phase shifter integrated with a low-noise amplifier (LNA) and power amplifier (PA) in a 65 nm CMOS technology for phased array systems. The 4-bit digitally controlled RF phase shifter is based on programmable weighted combinations of I/Q paths using digitally controlled variable gain amplifiers (VGAs). With the combination of an LNA, a phase shifter and part of a combiner, each receiver path achieves 7.2 dB noise figure, a 360° phase shift range in steps of approximately 22.5°, an average insertion gain of 12 dB at 61 GHz, a 3 dB-bandwidth of 5.5 GHz and dissipates 78 mW. Consisting of a phase shifter and a PA, one transmitter path achieves a maximum output power of higher than +8.3 dBm, a 360° phase shift range in 22.5° steps, an average insertion gain of 7.7 dB at 62 GHz, a 3 dB-bandwidth of 6.5 GHz and dissipates 168 mW.

A 9.8-11.5 GHz quadrature ring oscillator for optical receivers

A 9.8-11.5 GHz quadrature ring oscillator for use in the data clock recovery circuit of optical receivers has been realized in a BiCMOS technology with 30 GHz cut-off frequency. The circuit implementation of the oscillator uses active inductors which provide isolation between the oscillator and cascaded circuits such as buffers and flip-flops. Carrier to noise ratios better than 94 dBc/Hz at 2 MHz offset are measured with 75 mW dissipation and 2.7 V supply voltage. The realized quadrature oscillator achieves a state of the art oscillation frequency over transistor cut-off frequency ratio of 0.38.

Adaptive Impedance-Matching Techniques for Controlling L Networks

The link quality of mobile phones suffers from antenna mismatch due to fluctuating body effects. Techniques for adaptive control of impedance-matching L networks are presented, which provide automatic compensation of antenna mismatch. To secure reliable convergence, a cascade of two control loops is proposed for independent control of the real and imaginary parts of impedance. A secondary feedback path is used to enforce operation into a stable region when needed. These techniques exploit the basic properties of tunable series and parallel LC networks. A generic quadrature detector that offers a power-independent orthogonal reading of the complex impedance value is presented, which is used for direct control of variable capacitors. This approach renders calibration and elaborate software computation superfluous and allows for autonomous operation of adaptive antenna-matching modules.

A 14 bit 200 MS/s DAC With SFDR >78 dBc, IM3 < -83 dBc and NSD <-163 dBm/Hz Across the Whole Nyquist Band Enabled by Dynamic-Mismatch Mapping

This paper presents a 14 bit 200 MS/s current-steering DAC with a novel digital calibration technique called dynamic-mismatch mapping (DMM). By optimizing the switching sequence of current cells to reduce the dynamic integral nonlinearity in an I-Q domain, the DMM technique digitally calibrates all mismatch errors so that both the DAC static and dynamic performance can be significantly improved in a wide frequency range. Compared to traditional current source calibration techniques and static-mismatch mapping, DMM can reduce the distortion caused by both amplitude and timing mismatch errors. Compared to dynamic element matching, DMM does not increase the noise floor since the distortion is reduced, not randomized. The DMM DAC was implemented in a 0.14 μm CMOS technology and achieves a state-of-the-art performance of SFDR >; 78 dBc, IM3 <; -83 dBc and NSD <; -163 dBm/Hz in the whole 100 MHz Nyquist band.

Fully-integrated DECT/Bluetooth multi-band LNA in 0.18 /spl mu/m CMOS

The design of a multi-band low noise amplifier (LNA) is the first obstacle towards the design of a multi-standard receiver. In this paper, an approach for the design of a multi-band LNA for DECT and Bluetooth is presented. The formula for a minimal noise factor of a LNA, that takes into account the finite quality factor of the inductors is derived and the full design procedure that facilitates the design of a fully integrated LNA is given. The main advantages of the presented multi-band LNA are: high level of integration, reduced chip area by using only one integrated inductor, while the other is implemented as a bond-wire, input matching at two frequencies while having low noise figure, moderate voltage gain and good linearity. In DECT mode the simulated LNA performance is: NF = 2.2 dB, gain = 17 dB, IIP3 = 0.5 dBm, with a current of 8 mA, while in Bluetooth mode the LNA achieves: NF = 2.3 dB, gain = 15 dB, IIP3 = 3 dBm, with a current of only 4 mA.

Sigma-delta modulators operating at a limit cycle

A new type of sigma-delta modulator that operates in a special mode named limit-cycle mode (LCM) is proposed. In this mode, most of the SDM building blocks operate at a frequency that is an integer fraction of the applied sampling frequency. That brings several very attractive advantages: a reduction of the required power consumption per converted bandwidth, an immunity to excessive loop delays and to digital-analog converter waveform asymmetry and a higher tolerance to clock imperfections. The LCMs are studied via a graphical application of the describing function theory. A second-order continuous time SDM with 5 MHz conversion bandwidth, 1 GHz sampling frequency and 125 MHz limit-cycle frequency is used as a test case for the evaluation of the performance of the proposed type of modulators. High level and transistor simulations are presented and compared with the traditional SDM designs.

Adaptive methods to preserve power amplifier linearity under antenna mismatch conditions

Under antenna mismatch conditions at high output power, voltage clipping (due to collector voltage saturation) is the main cause of power amplifier linearity degradation. To preserve linearity under mismatch three adaptive methods are presented that make use of the detected minimum collector peak voltage. This detected signal controls either the amplifier output power, load-line, or supply voltage. These concepts are generalized analytically, and calculated results compare well to simulations. Measurements demonstrate am error vector magnitude reduction of 5% and an adjacent channel power ratio improvement of 10 dB at a voltage standing wave ratio of 4 for an EDGE amplifier with adaptively controlled output power. These adaptive methods offer a cost and size effective alternative to the use of an isolator.