Jaber Derakhshandeh

3D stacking of Co- and Ni-based microbumps

In this paper,the wettability, quality of joint formation and electrical yield of daisy chains in 3D stacks when using Cobalt and Nickel as UBM with different finish layers such as immersion Au, ELD NiB, ELD Cu and SAM are investigated. The performance of the stacks are characterized by cross-section SEM images, EDS analysis and electrical resistance measurement of the daisy chains.

Fine Pitch Rapid Heat Self-Aligned Assembly and Liquid-Mediated Direct Bonding of Si Chips

3-D stacking with vertical interconnection of thinned microelectronic silicon chips is a novel approach to achieve the enhanced performance, higher density, and smaller size of integrated circuits with a better multifunctionality than the traditional 2-D chip packaging. To achieve this, high alignment accuracy is required between the top chip and the bottom substrate along with good bonding between the two intermediate surfaces. In this paper, a novel approach to stacking is proposed: rapid heating self-aligned assembly. Using this approach, fast and good intermediate dielectric bonding is realized along with high alignment accuracy between the top chip and the bottom substrate compared with the similar process at room temperature. This approach can be used for die-to-die bonding and die-to-wafer bonding for 3-D and MEMS applications.

Physics of self-aligned assembly at room temperature

Self-aligned assembly, making use of capillary forces, is considered as an alternative to active alignment during thermo-compression bonding of Si chips in the 3D heterogeneous integration process. Various process parameters affect the alignment accuracy of the chip over the patterned binding site on a substrate/carrier wafer. This paper discusses the chip motion due to wetting and capillary force using a transient coupled physics model for the two regimes (that is, wetting regime and damped oscillatory regime) in the temporal domain. Using the transient model, the effect of the volume of the liquid and the placement accuracy of the chip on the alignment force is studied. The capillary time (that is, the time it takes for the chip to reach its mean position) for the chip is directly proportional to the placement offset and inversely proportional to the viscosity. The time constant of the harmonic oscillations is directly proportional to the gap between the chips due to the volume of the fluid. The predict...

3D stacking cobalt and nickel microbumps and kinetics of corresponding IMCs at low temperatures

To improve the performance of 3D electronic chips, dense I/O and interconnects are required. Increasing the density of interconnects requires smaller pitch micro-bumps. However, when scaling down microbumps several challenges have to be taken into account. Lithography of dense and high aspect ratio bump, wet etching of seed and barrier layer, solder volume and intermetallics (IMC) formation are some of the challenges that needs to be addressed. With reducing bump dimensions, solder volume decreases as well, converting Sn to complete IMC during the Thermo-Compression-Bonding (TCB) process. Full IMC formation increases stress in the joint, leading to crack formation and a brittle connection. Beside concerns about the IMC layer, the UBM (under bump metallization) consumption by the solder has to be addressed as well. Therefore, it is important to select the right UBM and solder to have enough Sn and UBM left in the joint for the time the product is working at a specific temperature [1].

Growth rate of IMC in the binary sytems of Co/Sn and Cu/Sn

In this study we discuss superiority of Cobalt for using in 3D interconnection as alternative metal to Cu. Specimens composed of pure Sn and Co or Cu is aged under same aging condition varied time and temperature below melting point of Sn. Thickness of IMC (intermetallic compound) formed at the interface is then calculated for extraction of growth rate and kinetics like activation energy and power factor. Compared with each factors extracted from calculation, IMC formation and growth of Co/Sn has stronger time and temperature dependence than IMC of Cu/Sn. Furthermore, no voids was observed at any interface in Co/Sn bonding.

Investigation of Co Thin Film as Buffer Layer Applied to Cu/Sn Eutectic Bonding and UBM With Sn, SnCu, and SAC Solders Joints

The demand of small-feature-size, high-performance, and dense I/O density applications promotes the development of fine-pitch vertical interconnects for 3-D integration where microbumps are fabricated with Cu through-silicon via and under-bump metallization. Small dimension Cu/Sn bonding has to be developed to address the needs of increasing I/O density and shrinking pitch and size for future applications. For fine-pitch microbumps, it is important to select right UBM and solder materials to obtain lower UBM consumption, which means lower intermetallic compound (IMC) thickness. To find the best binary system material for fine-pitch microbumps with a different annealing temperature and time, we investigate the interfacial reaction and intermetallic compound morphologies of Co UBM with Sn, SnCu, and SAC solders. A thin, uniform, and single-phase IMC between solder and UBM facilitates finer pitch and more reliable microbumps development; the higher activation energies imply longer solder lifetime. Co, as an ultrathin buffer layer (UBL), is also used in Cu/Sn bonding. A comparison between Cu–Sn bonding with and without UBL is conducted. From this study, Co as UBL and UBM is explored and could be applied in semiconductor applications.

Impact of ELD layers in mechanical properties of microbumps for 3D stacking

In this paper the influence of adding ELD barrier and capping layers in die shear strength of 3D stacked chips is discussed. Electroless NiB is used as barrier layer to prevent solder or UBM consumption and immersion Au is used as capping layer to improve the solder wettability. In this study UBM layers are Cu, Co and Ni and pure Sn is used as solder. For bonding both reflow and TCB methods are employed. Mechanical properties of bonded 3D stacks with different UBM/solder systems are characterized by die shear test followed by SEM and EDX analysis for fracture location and mechanism identifications.

Surface Treatment to Enable Low Temperature and Pressure Copper Direct Bonding

One of the major area of interest of the electronics packaging industry is the formation of interconnects between the chips in a 3D package. Copper has been proven to be a suitable candidate for the conductive material in back-end-of-line due to its low electrical resistivity and high electro-migration resistance. Due to this favorable property of copper, it is also used to form microbumps and through silicon vias (TSVs) for 3D stacking. To stack known good dies (KGDs), die-to-die (D2D) and die-to-wafer (D2W) bonding are the traditional approaches used in 3D stacking. Flip chip thermo-compression bonding (TCB) is employed to enable a joint formation between the microbumps of the top chip and the bottom substrate. Most TCB tools are limited by pressure and temperature parameters. High temperature and pressure requirements make the bonding process costly and may cause additional reliability concerns. Good joint formation at low temperature and low pressure is preferred to address these issues for various applications. The aim of this paper is to explore different dry and wet cleaning approach to understand its effect on the copper surface and its effect to enable low temperature (250 °C) and low pressure (~23 MPa) bonding in a cleanroom environment without compromising the joint quality.

Liquid mediated direct bonding and bond propagation

Room temperature and pressure bonding is shown for wafer-to-wafer (W2W) bonding but never for small chips. Usually, thermo-compression bonding (TCB) is employed for die-to-die (D2D) and die-to-wafer (D2W) bonding for 3D and MEMS application. TCB process is itself limited by tool capability and requires pressure and temperature for bonding which is not only time consuming but can induce coefficient of thermal expansion mismatch and damage to back-end-of-line (BEOL) stacks. To address these issue, we propose a liquid mediated direct bonding approach of inorganic dielectric which can be realized at low temperature and atmospheric pressure using a fast pick and place tool.

Thiol‐Based Self‐Assembled Monolayers (SAMs) as an Alternative Surface Finish for 3D Cu Microbumps

With scaling beyond 40um pitch 3D interconnects, cost, performance and reliability become ever more critical. Thiol-based self-assembled monolayers (SAM) were applied before to enable Cu-Cu connection in dual damascene vias [1]. In this study, we are researched a parallel application, for an alternative, low-cost organic surface finish for electroplated Cu pads/pillar/bumps to enable 3D interconnects [2]. The effects of pre-cleaning, deposition times and self-assembled monolayer (SAM) type (C3, C10, C18) on oxidation resistance and electrical continuity were studied with Voltammetry and X-ray Photoelectron Spectroscopy (XPS). Experiments were performed on electroplated Cu flat samples and process conditions were selected for further processing of 3D patterned dies and subsequent stacking and thermo-compression bonding in a face-to-face configuration. Overall, C18 SAM showed better electrical continuity and lower electrical resistance than C3 and C10, a result which is consistent with the longer C chain and higher thermal stability of C18. A second result of this study — consistent in both flat and patterned samples — was that microwave plasma cleaning prior to SAM deposition was more effective than wet cleaning, indicating either better oxide cleanability or better affinity of SAM’s with more pristine Cu.