Wei-Ching Wang

Impact of source/drain Si1-yCy stressors on silicon-on-insulator N-type metal-oxide-semiconductor field-effect transistors

The stress field in the channel of a silicon-on-insulator (SOI) N-type metal–oxide–semiconductor field-effect transistor (NMOSFET) with silicon–carbon alloy source and drain stressors was evaluated. The physical origin of the stress components in the transistor channel region was explained. The magnitude and distribution of the strain components, and their dependence on device design parameters such as the spacing between the silicon–carbon alloy stressors, the carbon mole fraction in the stressors and stressor recessed depth and raised height were investigated. The reduction in the stressor spacing or increase in the carbon mole fraction of the stressors and the stressor recessed depth and raised height increase the magnitude of the vertical compressive stress and the lateral tensile stress in the portion of the channel region where the inversion charge exists. This is beneficial for improving the electron mobility in NMOSFETs. A simple guiding principle for an optimum combination of the above-mentioned device design parameters and the trade-off between performance and junction leakage current degradation is discussed in this paper.

Impact of channel width and dummy length on performance enhancement in p-type metal oxide semiconductor field effect transistor with a silicon-germanium alloy stressor

The stress distribution in the Si channel regions of silicon-germanium (SiGe) source/drain p-type metal oxide semiconductor field effect transistor of various widths and dummy lengths was studied using ANSYS simulations. The drain current enhancement is dominated by the compressive stress along the transport direction. Stress perpendicular to the channel was found to have the least effect on the drain current in wide-width devices. However, this stress component cannot be neglected in narrower devices. The tensile stress along the vertical direction contributes to the drain current enhancement in wide devices but can be neglected when the width is very small. The impact of channel width and dummy length effects on improvements in device performance such as the drive current gain was also analyzed.

A Simulation Study of Oxide Thickness Effect on the Performance of SiGe HBTs with SOI Structure

Using a TCAD simulator, we examine the oxide thickness effect on electrical characteristics of the SiGe HBT on SOI substrates. We have investigated this effect on Early voltage, cut-off frequency, and maximum oscillation frequency for SiGe HBT on SOI substrate. It is found that the maximum oscillation frequency (fmax) of SiGe HBT on SOI substrate is much better than that of conventional SiGe HBT. The maximum oscillation frequency increases with the increase in oxide thickness and tend to saturate at oxide thickness of 0.15 mum. In order to study oxide thickness on self-heating effect, thermal resistances are also simulated.

Technology CAD simulation study for self-heating effects in Si/SiGe HBTs on thin-film SOI substrates

The self-heating characteristic of Si/SiGe HBTs on thin-film SOI substrate is investigated by a technology CAD simulator. We examine both of the buried-oxide thickness and the silicon thickness effects on the device characteristics for thermal resistance. Simulation results show that the self-heating effect is not serious for the device under the situation of smaller oxide thickness. Besides, the enhanced silicon thickness can degrade the thermal resistance and thus needs to be carefully considered in device design. The thermal resistance characteristics revealed for Si/SiGe HBTs on thin-film SOI substrate may help to establish more accurate thermal model for reliability of circuit design and device technology optimization.

High efficient Si nano-textured light-emitting diodes and solar cells with obvious photonic crystal effect

The light-emission efficiency in Si light-emitting diodes with nano-scale trench structure on the top surface can be enhanced about 10 times than it in the control device. The photonic crystal effect, the characteristics of the wavelength extraction, is also observed easily and it agrees well with the theoretical surface plasma calculation. In addition to the application of nano-scale textured surface structure for the light-emitting diode, the nano-textured surface Si solar cell is also observed and investigated to have the higher open-circuit voltage, short circuit current, and optic-electric transformation efficiency, due to the light trapping, low reflection on the nano-textured surface, and more carriers collected in the larger n/p junction area. The efficiency can successfully be improved about 2.9% (from 12% to 14.9%) by the nano-surface structure. These experimental results prove that the dimension of the surface structure on the Si photonic device is worthy to continuously scale down to the nano-meter scale; even the current device structure is in the order of the micro-meter scale level.

Carrier backscattering characteristics of nanoscale strained complementary metal-oxide-semiconductor devices featuring the optimal stress engineering

The authors present stress distribution simulation characterization of the three-dimensional boundary effects and show how these effects can impact the achievable transistor performance gain. The high-performance complementary metal-oxide-semiconductor (CMOS) device has been achieved by stressors such as contact etch stop layer (CESL) and SiGe S/D and optimal geometric structure design. The biaxial-like stress distribution resulting from symmetry structure and uniaxial-like stress distribution resulting from asymmetry structure seems to be promising when considering drive current enhancement, the ballistic efficiency, and carrier injection velocity for CMOS devices. The comprehensive study helps the future nanoscale CMOS device design and demonstrates that the stress enhancement factors remain valid for future technology.

Impact of width effect on performance enhancement in NMOSFETs with silicon-carbon alloy stressor and stress CESL

We simulated stress components in three directions in the Si channel of NMOSFETs with SiC alloy S/D stressor and tensile CESL in this study. The resulting saturation drain current enhancement was analyzed. Tensile stress along the transport direction was found to dominate mobility enhancement. Stress along the width direction was found to affect drain current the least. However, for NMOSFETs, the compressive stress along vertical direction perpendicular to the gate oxide the makes considerable contribution to mobility enhancement and can not be neglected. To obtain the new mobility model for this study, we extended a simple model for strain effect in Si band, to include both shear strain and the quantum confinement effect in the inversion layer of NMOSFETs.

3D Simulations of Width Effect on Performance in NMOSFETs with SiC S/D Stressors and CSEL Linear

Stress distribution in the Si channel regions of SiC source/drain NMOSFETs with various widths is studied by 3D simulations. The impact of width on performance improvement is analyzed.

Novel Flash Memory Cell with a Channel Multi-Gate Transistor

W. –C. Wang, Y. -H. Ko, M. Tang, and S.T. Chang Dept. of Electronic Engineering, Chung Yuan Christian University, Chung-Li, Taiwan, ROC, ProMos Technologies, No. 19, Li-Hsin Rd., Science-Based Industrial Park, Hsin-Chu, Taiwan, ROC, Dept. of Electrical Engineering, National Chung-Hsing University, Tai-Chung, Taiwan, ROC, TEL: 886-4 -22851549 ext 702 FAX: 886-4-22851410, and Email: stchang@dragon.nchu.edu.tw