Jae-Kyu Lee

Verification on the extreme scalability of STT-MRAM without loss of thermal stability below 15 nm MTJ cell

Scalability of interface driven perpendicular magnetic anisotropy (i-PMA) magnetic tunnel junctions (MTJs) has been improved down to 1X node which verifies STT-MRAM for future standalone memory. With developing a novel damage-less MTJ patterning process, robust magnetic and electrical performances of i-PMA MTJ cell down to 15 nm node could be achieved.

High-performance cell transistor design using metallic shield embedded shallow trench isolation (MSE-STI) for Gbit generation DRAM's

In this paper, the cell transistor design issues for the Gbit level DRAMs with the isolation pitch of less than 0.2 /spl mu/m caused by the inverse-narrow-channel effect (INCE) and the neighboring storage-node E-field penetration effect (NSPE) will be discussed. Then we propose novel DRAM cell transistor structure by employing metallic shield inside the shallow trench isolation (STI). As confirmed by three-dimensional (3-D) device simulation results, by suppressing the inverse narrow-channel effect and the neighboring storage-node E-field penetration effect using metallic shield inside STI, we can obtain reliable cell transistors with low-doped substrate, low junction leakage current and uniform V/sub TH/ a distribution regardless of the active width variation.

The impact of isolation pitch scaling on V/sub TH/ fluctuation in DRAM cell transistors due to neighboring drain/source electric field penetration

This paper presents the accelerated inverse narrow channel effect of DRAM cell transistors caused by lateral E-field penetration from drain/source junctions of neighboring cell transistors. This phenomenon strongly increases the threshold voltage fluctuation of cell transistors depending on the junction biases of neighboring cell transistors and will impose physical size and the voltage scaling constraints for the Gigabit level DRAM technology.

High Performance Cell Transistor for Long Data Retention Time in Giga-bit Density Dynamic Random Access Memory and Beyond

High performance cell transistor was proposed for long data retention time in mass-produced 512 Mb dynamic random access memory (DRAM) with 0.12 µm design rule. Since process-induced trap density and electric field at the storage node junction should be reduced to improve data retention time, we designed a cell transistor using localized channel and field implantation (LOCFI) scheme. Using LOCFI scheme, the data retention time was nearly doubled by virtue of reduced cell leakage current resulting from the suppressed ion implantation damage and the reduced electric field at the storage node simultaneously. In addition, it was found that the hydrogen annealing after trench etching, the double gate spacer consisting of CVD oxide and Si3N4 layer, and the chemical downstream Si treatment after storage node contact etching significantly improved the data retention time. These proposed approaches for longer data retention time can be applied to future high density DRAMs with feature size down to 0.1 µm range.