Jae-pil Shin

Interlayer design verification methodology using contour image

Memory industry has been pursuing endless shrinking technology which increases fabrication complexity. It poses problems between adjacent layers as well as within a single layer. To verify the interlayer design, we have developed the interlayer design verification methodology using contour image. Our methodology makes it possible to verify interlayer design visually by extracting the contour image from the real patterns. And we can verify interlayer design even during the fabrication process and conduct a non-destructive inspection. Also this methodology provides a statistical analysis of massive measured data. Through this methodology, we can calculate the margin of current interlayer design and suggest the requirement of design.

Fast layout processing methodologies for scalable distributed computing applications

As the feature size shrinks to sub-20nm, more advanced OPC technologies such as ILT and the new lithographic resolution by EUV become the key solutions for device fabrication. These technologies leads to the file size explosion of up to hundreds of gigabytes of GDSII and OASIS files mainly due to the addition of complicated scattering bars and flattening of the design to compensate for long range effects. Splitting and merging layout files have been done sequentially in typical distributed computing layout applications. This portion becomes the bottle neck, causing the scalability to become poor. According to the Amdahls law, minimizing the portion of sequential part is the key to get the maximum speed up. In this paper, we present scalable layout dividing and merging methodologies: Skeleton file based querying and direct OASIS file merging. These methods not only use a very minimum memory footprint but also achieve remarkable speed improvement. The skeleton file concept is very novel for a distributed application requiring geometrical processing, as it allows almost pseudo-random access into the input GDSII or OASIS file. Client machines can make use of the random access and perform fast query operations. The skeleton concept also works very well for flat input layouts, which is often the case of post-OPC data. Also, our OASIS file merging scheme is a smart approach which is equivalent of a binary file concatenation scheme. The merging method for OASIS files concatenates shape information in binary format with basic interpretation of bits with very low memory usage. We have observed that the skeleton file concept achieved 13.5 times speed improvement and used only 3.78% of memory on the master, over the conventional concept of converting into an internal format. Also, the merging speed is very fast, 28MB/sec and it is 44.5 times faster than conventional method. On top of the fast merging speed, it is very scalable since the merging time grows in linear fashion with respect to the file size. Our experiment setup includes hundreds of gigabytes of GDSII and OASIS files. We demonstrate in the paper, that the skeleton file based querying and direct OASIS file-merging schemes are very scalable for distributed computing applications for large volume layout. Additionally, we used embedded skeleton file scheme to improve file loading speed in layout viewer system and achieved 61 time speedup. We used Nirmaan, SoftJins post-layout EDA toolkit for skeleton file based querying, OASIS file-merging and embedded skeleton file schemes.

A novel pattern error detecting algorithm for SEM images of mask monitoring patterns

In mask fabrication, e-beam exposure equipment malfunctioning could produce erroneous masks, several consecutive mask failures in the worst case. This type of error might unexpectedly increase mask turnaround time. Due to high cost of mask fabrication and its annual growth, it is critical detecting those errors as early as possible. Since mask SEM images at after-development inspection (ADI) phase have more visible noise, edges might be hard to detect clearly using classical edge detection algorithms. In this context, we present a novel pattern error detecting algorithm to capture pattern errors in mask monitoring patterns by inspecting mask SEM images at ADI phase. The originality of this paper lies in its use of simple but powerful techniques in a series used for automated error detection. More specifically, we inspect two specific types of errors in SEM images of monitoring patterns: bridging errors in a chessboard pattern, and CD uniformity errors in a line-and-space pattern. For a chessboard pattern, we utilize both horizontal and vertical projections of image intensity histogram to find areas for inspection automatically. From one dimensional projection of the image, we identify spatial coordinates of our interests, and define a small rectangular region, called D-region. For each D-region, we determine whether a pattern bridge is likely to occur, based on the ratio of brighter pixels in it. For a line-and-space pattern, we compute base lines for CD measurement, and detect CD uniformity errors or line shift errors by applying similar one dimensional histogram analysis and CD-computation algorithm to the image. Our experimental results using real pattern images and programmed defect images support that this technique is effective and robust in detecting errors without layout data or another SEM image for comparison.

Global pattern density control by resizing fill patterns for CD skew compensation

The global pattern density of a mask is a major factor of etch process-induced CD skew. Logic products have different global pattern densities according to the various area portions of SRAM and logic cells. For example, the pattern densities of 66 devices of 130nm node vary from 34% to 47.7% for active layer and from 14.7% to 26.7% for gate poly layer. In order to compensate the global pattern density effect on CD skew, the process condition change is easy to practice for process engineers. But the process condition change for each device increases process variation and reduces process margin. A direct approach to compensate the global density effect on CD skew is necessary. In this paper, we propose a method to make the global pattern density of a mask uniform at the data preparation stage. Our approach is to resize fill patterns to control the global pattern density. We confirmed that the proposed method is effective to control the global pattern densities of masks to a target density within +/- 1%.

A memory efficient large mask data handling method using repetition

After model-based OPC and layer generation, the size of mask data is increasing beyond the limit that current software and hardware can handle. The file size of one of 512M DRAM mask data was 29 GB in GDSII and it could be reduced to 1.7 GB by transforming into OASIS. Compared to GDSII, OASIS included many effective features that could reduce the file size incredibly. In this paper, we adopted the repetitions in OASIS and used the concept to reduce the memory usage of mask data preparation software. We built a new data structure, called shape array that utilizes the repetition of mask data. Mask data is saved in OASIS and its repetition information is loaded onto memory. The data structure can be the basis for the mask data preparation operations such as region query, AND, XOR and so on. We implemented the region query in this paper. The region query is a major operation that a layout viewer uses. The mask data comparison operation, which is used to check the integrity of the mask data, is implemented with the shape array as well. The shape array method has used the memory of between 2 and 22 times less than the method that keeps the coordinate and attributes of each shape individually. The file loading time and the file writing time have improved 4~73 times and 1.5~14 times, respectively.

Chip level lithography verification system with artificial neural networks

The lithography verification of critical dimension variation, pinching, and bridging becomes indispensable in synthesizing mask data for the photolithography process. In handling IC layout data, the software usually use the hierarchical information of the design to reduce execution time and to overcome peak memory usage. However, the layout data become flattened by resolution enhancement techniques, such as optical proximity correction, assist features insertion, and dummy pattern insertion. Consequently, the lithography verification software should take burden of processing the flattened data. This paper describes the hierarchy restructuring and artificial neural networks methods in developing a rapid lithography verification system. The hierarchy restructuring method is applied on layout patterns so that the lithography verification on the flattened layout data can attain the speed of hierarchical processing. Artificial neural networks are employed to replace lithography simulation. We define input parameters, which is major factors in determining patterns width, for the artificial neural network system. We also introduce a learning technique in the neural networks to achieve accuracy comparable to an existing lithography verification system. Failure detection with artificial neural networks outperforms the methods that use the convolution-based simulation. The proposed system shows 10 times better performance than a widely accepted system while it achieves the same predictability on lithography failures.

Efficient mask data preparation for variable shaped e-beam writing system focusing on memory devices

To cope with sub-100nm technology in the mask making industry, a variable shaped e-beam(VSB) writing system is one of the solutions through its high-electron voltage. The VSB writing system, however, requires a different mask data preparation comparing to the traditional raster scan writing system. Due to the differences, mask making industries are confronted with difficult problems, such as explosively increasing data volume and unpredictably growing mask making time especially for memory devices. VSB systems writing time is determined by the conversion from CAD data to VSB data. The conversion time, especially for the critical layers of memory devices, mostly depends on to what extent optimize CAD data to enhance writing system throughput. For this reason, to shorten the unpredictably growing mask making time, a data conversion tool must consider the throughput of data conversion and mask writing at the same time. To reduce the data conversion time while retaining the optimal writing time, we propose the mixed-mode data processing method, in which the hierarchical data operation is applied on memory cells and the flat data operation is applied on peripheral circuits. For each area, different fracturing strategies are applied, too. The polygon-aware fracturing method is applied to improve the CD control within memory cells, and the selective one-directional fracturing method is applied to reduce the writing time within peripheral circuits.