Moon-han Park

Void free and low stress shallow trench isolation technology using P-SOG for sub 0.1 /spl mu/m device

Highly reliable void free shallow trench isolation (VF-STI) technology by employing polysilazane based inorganic spin-on-glass (P-SOG) is developed for sub-0.1 /spl mu/m devices. In order to overcome the difficulties from the gap-filling and accumulated mechanical stress in STI, a P-SOG pillar is introduced at the trench bottom. As a result, the P-SOG pillar, having low stress, improves data retention time and hot carrier immunity in 256 Mbit DRAM by reducing cumulative STI stress. In addition, VF-STI shows an excellent extendibility in terms of gap filling capability even at an aspect ratio of more than 10 without void formation.

Ultimate solution for low thermal budget gate spacer and etch stopper to retard short channel effect in sub-90 nm devices

For the first time, by employing low thermal budget processes of ALD SiO/sub 2/ and ALD SiN as gate spacer and silicide blocking layer, the short channel effects of CMOSFETs are significantly suppressed. Using the ALD SiO/sub 2/ and ALD SiN processes, we achieved excellent roll-off characteristics of threshold voltage in PMOS, which results in 10% increase of drive current and 15% decrease of inverter delay time. Furthermore, gate oxide reliability and static noise margin of 6T-SRAM bit cell with ALD SiC/sub 2/SiN processes are comparable to those with conventional high temperature CVD SiO/sub 2//SiN processes. In conclusion, ALD SiO/sub 2/ and ALD SiN processes of extremely low thermal budget are successfully implemented to sub-90 nm CMOSFETs.

A novel simple shallow trench isolation (SSTI) technology using high selective CeO/sub 2/ slurry and liner SiN as a CMP stopper

A novel simple shallow trench isolation technology, SSTI, has been developed. SSTI consists of direct trench etching masked only with the photoresist, trench oxidation, liner SiN deposition, CVD oxide trench fill, densification, and high selectivity CMP. CMP stops at the liner SiN with a residual SiN thickness range of less than 2 nm and without micro-scratching. High selectivity CMP eliminates the field recess variation which is one of the drawbacks of conventional STI. SSTI is a promising candidate for future isolation technology.

High quality high-k MIM capacitor by Ta/sub 2/O/sub 5//HfO/sub 2//Ta/sub 2/O/sub 5/ multi-layered dielectric and NH/sub 3/ plasma interface treatments for mixed-signal/RF applications

Novel high-k MIM capacitor technology for mixed-signal/RF applications has been successfully developed by introducing multilayered high-k dielectric(Ta/sub 2/O/sub 5//HfO/sub 2//Ta/sub 2/O/sub 5/) and NH/sub 3/ plasma electrode-dielectric interfaces treatments. For the first time, we have simultaneously achieved high capacitance of 4fF/um/sup 2/ and low leakage current of 100nA/cm/sup 2/ at high temperature of 125/spl deg/C with ultra low VCC(a=16.9ppm/V/sup 2/, b=5.2ppm/V) and high Q(/spl sim/107 at 2.4GHz and 5.4pF).

Novel plasma enhanced atomic layer deposition technology for high-k capacitor with EOT of 8 /spl Aring/ on conventional metal electrode

We have developed a plasma enhanced atomic layer deposition(PEALD) technology for high-k dielectrics such as Al/sub 2/O/sub 3/,Ta/sub 2/O/sub 5/ and HfO/sub 2/. Film quality and throughput of PEALD are far superior to that of ALD which has been spotlighted as a deposition technology for next generation semiconductor devices. We have obtained a extremely low equivalent oxide thickness(EOT) of 8 /spl Aring/ from HfO/sub 2/ film, which has not been reported in conventional metal-based memory capacitors up to now. It was confirmed that PEALD-Al/sub 2/O/sub 3/ and Ta/sub 2/O/sub 5/ films are superior to those using any other deposition techniques and very useful as System-on-Chip(SoC) capacitors.