Dong-ho Ahn

High performance PRAM cell scalable to sub-20nm technology with below 4F2 cell size, extendable to DRAM applications

A PRAM cell with great scalability and high speed operation capability with excellent reliability below 20nm technology was demonstrated. This has the meaning of the potential applicable to the technology area of scaling limitation of DRAM cell. We fabricated a confined PRAM cell with 7.5nm×17nm of below 4F2. In particular, Sb-rich Ge-Sb-Te phase change material was employed for high speed operation below 30nsec. The excellent writing endurance performance was predicted to maintain up to 6.5E15cycles by reset program energy acceleration. Its data retention was 4.5 years at 85°C which is enough for DRAM application.

PRAM cell technology and characterization in 20nm node size

We reported characteristics of 20nm PRAM cell. Optimization of diode integration process and improved implantation technology were used to satisfy the required diode on-current (Ion) with low off-current (Ioff). Confined cell structure and novel bottom electrode (BE) materials were developed to reduce a reset current (Ireset) below 100uA. Using the advanced technologies, we successfully produced fully integrated 20nm node size PRAM device for the first time.

A unified 7.5nm dash-type confined cell for high performance PRAM device

We present a new-type confine structure within 7.5 nm width dash-contact for sub 20 nm generation PRAMs. Phase change material (PCM) by chemical vapor deposition (CVD) was perfectly filled in a 7.5 nm width dash-contact without void along with 30 nm depth. By adopting confined CVD-PCM, we were able to reduce the reset current below ~160 muA and to obtain high reliability. In addition, the programming time of dash-confined cell was much improved to 50 ns due to volume confinement of PCM cell. Consequently, we firstly demonstrate the high performance of the 7.5 nm width confined cell, which is the smallest size close to physical limit.

Scalable High-Performance Phase-Change Memory Employing CVD GeBiTe

We first present chemical-vapor-deposited GeBiTe (CVD GBT) in a confined cell for high-performance phase-change random access memory (PRAM). Due to the fast crystallization of GBT, we were able to reduce the speed to less than 26 ns while maintaining endurance characteristics up to 109 cycles. Our results indicate that the scalable PRAM device enabling the use of PRAM in dynamic RAM and storage class memory applications can be realized using CVD GBT.

Reduction of RESET current in phase change memory devices by carbon doping in GeSbTe films

Phase Change Memory (PCM) has been proposed for use as a substitute for flash memory to satisfy the huge demands for high performance and reliability that promise to come in the next generation. In spite of its high scalability, reliability, and simple structure, high writing current, e.g., RESET current, has been a significant obstacle to achieving a high density in storage applications and the low power consumption required for use in mobile applications. We report herein on an attempt to determine the level of carbon incorporated into a GeSbTe (GST) film that is needed to reduce the RESET current of PCM devices. The crystal structure of the film was transformed into an amorphous phase by carbon doping, the stability of which was enhanced with increasing carbon content. This was verified by the small grain size and large band gap that are typically associated with carbon. The increased level of C-Ge covalent bonding is responsible for these enhancements. Thus, the resistance of the carbon doped Ge2Sb2Te...

A highly practical modified LOCOS isolation technology for the 256 Mbit DRAM

We have developed a modified LOCOS isolation technology for the 256 Mbit DRAM. This novel Poly-Si Spacer LOCOS (PSL) isolation has been applied to build a 16 Mbit density DRAM with 256 Mbit (0.3 /spl mu/m) design rules. With the PSL isolation process, low birds beak encroachment, good vertical profile, clear definition of the active and field boundaries, high punchthrough voltage, and low leakage current have been achieved by simple fabrication processes.<<ETX>>

Reliability perspectives for high density PRAM manufacturing

This paper discussed the key reliability issues for manufacturing high density phase change memory (PRAM). There are its own unique phenomena, such as resistance fluctuation, structural relaxation and crystallization, which are closely correlated with the device reliability characteristics, including data retention, cycling endurance, and write disturbance. Optimizing material composition and controlling doping concentration and minimizing variability of physical dimensions can improve the reliability issues. Above all, isotropic dimension scaling along with writing current scaling is essential for continuing scaling down below 20nm node.

Current status and future prospect of Phase Change Memory

This paper reviews recent progress and future outlook of PRAM as a promising candidate for emerging non-volatile memory. Electrical characteristics and reliability issues of PRAM with scale-down of the device dimension are discussed. Despite remarkable progress of PRAM properties in recent last decades, there are still several fundamental issues to resolve for broadening its application area. Several suggestions to overcome these property issues are introduced with recent experimental results.

Considerations on highly scalable and easily stackable phase change memory cell array for low-cost and high-performance applications

Needs for the performance improvement of memory subsystem in big data and clouding computing era begin to open new markets for emerging memories such as phase change memory, spin-torque-transfer magnetic memory, and metal oxide memory. To fulfill these needs, a cost-effective and high-speed phase change memory cell scheme was introduced at 19nm technology node, which is directly scalable down to 1y or 1z nm nodes and can be extendable to stacked array for higher density. Here, key technologies such as self-aligned cell patterning and vertical poly-Si diode switch on metal word line were adopted. In addition, damascene Ge-Sb-Te technologies were optimized to improve programming speed and to show excellent cell performances.

Enhancement of a cyclic endurance of phase change memory by application of a high-density C15(Ge21Sb36Te43) film

The lower cyclic endurance of Phase Change Memory (PCM) devices limits the spread of its applications for reliable memory. The findings reported here show that micro-voids and excess vacancies that are produced during the deposition process and the subsequent growth in sputtered carbon-doped GeSbTe films is one of the major causes of device failure in PCM with cycling. We found that the size of voids in C15(Ge21Sb36Te43) films increased with increasing annealing temperature and the activation energy for the growth rate of voids was determined to be 2.22 eV. The film density, which is closely related to voids, varies with the deposition temperature and sputtering power used. The lower heat of vaporization of elemental Sb and Te compared to that for elemental Ge and C is a major cause of the low density of the film. It was possible to suppress void formation to a considerable extent by optimizing the deposition conditions, which leads to a dramatic enhancement in cyclic endurance by 2 orders of magnitude in PCM devices prepared at 300oC-300W compared to one prepared at 240oC-500W without change of compositions.