Jaewon Nam

A 9-bit 80 MS/s Successive Approximation Register Analog-to-Digital Converter With a Capacitor Reduction Technique

A 9-bit 80 MS/s successive approximation register analog-to-digital converter (ADC), which is suitable for low power and a small area, is presented. The 9-bit capacitor array consists of only 16 unit capacitors and a coupling capacitor due to the proposed binary-weighted split-capacitor arrays with a merged-capacitor switching technique. The proposed ADC includes a comparator with offset cancellation and uses digital calibration for error correction. The ADC is implemented in a 65-nm complimentary metal-oxide-semiconductor technology and occupies an active area of 0.068 mm2 with a reference buffer. The differential and integral nonlinearities of the ADC are less than 0.37 and 0.40 LSB, respectively. The ADC shows a signal-to-noise-distortion ratio of 50.71 dB, a spurious-free dynamic range of 66.72 dB, and an effective number of bits of 8.13 bits with a 78 MHz sinusoidal input at 80 MS/s. The ADC consumes 3.4 mW with the reference buffer at a 1.0-V supply and achieves a figure of merit of 78 fJ/conversion step.

A Dual-Channel Pipelined ADC With Sub-ADC Based on Flash–SAR Architecture

This brief presents a 10-bit dual-channel pipelined flash-successive approximation register (SAR) analog-to-digital converter (ADC) for high-speed applications. The proposed ADC consists of two channels for high operating speed, and each channel adopts a pipelined flash-SAR architecture for low power and a small area. The proposed flash-SAR ADC in the second stage is composed of a 1-bit flash ADC and a 6-bit SAR ADC considering the chip area, operation speed, and circuit complexity. The prototype ADC fabricated in a 45-nm CMOS process occupies 0.16 mm2. The differential and integral nonlinearities of the ADC are less than 0.36 and 0.67 LSB, respectively. The ADC shows a signal-to-noise-and-distortion ratio of 54.6 dB and a spurious-free dynamic range of 64.0 dB with a 78-MHz input at 230 MS/s with a 1.1-V supply. The maximum operating frequency of the ADC is 260 MS/s at a 1.2-V supply. The power consumptions of the ADC with 230 and 260 MS/s are 13.9 and 17.8 mW, respectively.

A 12-bit 100-MS/s pipelined ADC in 45-nm CMOS

This paper presents a 12-bit 100-MS/s pipeline analog-to-digital converter (ADC) in a 45-nm CMOS technology. The low-voltage circuit techniques and a careful layout are adopted to obtain high-resolution in a low-supply. The ADC features 12-bit resolution, 100-MS/s sampling rate, differential nonlinearity (DNL) of ±0.58 LSB, integral nonlinearity (INL) of ±2.79 LSB, and power consumption of 30.4 mW. With a sampling frequency of a 100-MS/s and an input of a 2.4 MHz, the ADC achieves a signal to noise-and-distortion ratio and a spurious-free dynamic range of 59.02 dB and 63.22 dB, at a supply voltage of 1.1 V, respectively.

A 10-bit 30-MS/s successive approximation register analog-to-digital converter for low-power sub-sampling applications

A 10-bit 30-MS/s successive approximation register analog-to-digital converter (ADC), which is suitable for low-power sub-sampling applications, is presented. Bootstrapped switches are used to enhance the sampling linearity at the high input frequency. The proposed ADC adopts a binary-weighted split-capacitor array with the energy efficient switching procedure and includes an asynchronous clock scheme to yield more power and speed-efficiency. The ADC is fabricated in a 65nm complementary metal-oxide-semiconductor technology and occupies an active area of 0.07mm^2. The differential and integral nonlinearities of the ADC are less than 0.82 and 1.13 LSB, respectively. The ADC shows a signal-to-noise-distortion ratio of 56.60dB, a spurious free dynamic range of 73.35dB, and an effective number of bits (ENOB) of 9.11-bits with a 2.5-MHz sinusoidal input at 30-MS/s. It exhibits higher than 8.86 ENOB for input frequencies up to 78-MHz. The ADC consumes 0.85mW at a 1.1V supply and achieves a figure-of-merit of 51fJ/conversion-step.

A 2.85mW 0.12mm 2 1.0V 11-bit 20-MS/s algorithmic ADC in 65nm CMOS

An 11-bit 20-MS/s algorithmic analog-to-digital converter (ADC) based on a dynamic biasing technique is proposed. A dynamic biasing technique is employed to an operational transconductance amplifier (OTA) for power reduction in sub-conversion stages. Besides, a distinct sampling clock scheme is taken to pre-amplifier for reducing aperture time errors. The prototype ADC is fabricated in a 65nm 1P6M CMOS process and features a maximum signal-to-noise-ratio and a spurious-free-dynamic-range of 60.4dB, and 69.2dB at Nyquist input frequency with 20MS/s from a 1.0V supply, respectively. About 22% of OTA power dissipation is reduced without performance degradation and totally 2.85mW is consumed.

A 12-bit 200-MS/s pipelined A/D converter with sampling skew reduction technique

This paper presents a 12-bit 200-MS/s dual channel pipeline analog-to-digital converter (ADC). The ADC is featured with a digital timing correction for reducing a sampling skew and the capacitor swapping for suppressing nonlinearities at the first stage in the pipelined ADC. The prototype ADC occupies 0.8x1.4mm^2 in a 65-nm CMOS technology. The differential nonlinearity is less than 1.0 least significant bit with a 200MHz sampling frequency. With a sampling frequency of a 200-MS/s and an input of a 2.4MHz, the ADC, respectively, achieves a signal to noise-and-distortion ratio and a spurious-free dynamic range of 61.49dB-70.71dB while consuming of 112mW at a supply voltage of 1.1V.